Integrated circuit having built-in self-test features
An integrated circuit and a method of built-in self test in the integrated circuit employ an offset control node and offset capabilities with the integrated circuit in order to communicate and distribute a built-in self-test signal. The built-in self-test signal can emulate signals internal to the integrated circuit during normal operation, and/or the built-in self-test signal can have other signal characteristics representative of signals other than those signals internal to the integrated circuit during normal operation.
1. A method of built-in self-test in an integrated circuit, comprising:
communicating a built-in self-test control signal to the integrated circuit;
generating one or more analog self-test signals within the integrated circuit; and
coupling the one or more analog self-test signals to a respective one or more offset control nodes within the integrated circuit in response to the communicating.
2. The method of claim 1 , further comprising representing a proximity of a ferromagnetic object with a characteristic of at least one of the analog self-test signals.
3. The method of claim 1 , further comprising representing a rotation of a ferromagnetic object with a characteristic of at least one of the analog self-test signals.
4. The method of claim 3 , wherein the one or more analog self-test signals comprise a first analog self-test signal and a second analog self-test signal, wherein the method further comprises representing a direction of rotation of the ferromagnetic object with a relative phase between the first and second analog self-test signals.
5. The method of claim 4 , wherein the method further comprises representing a change of direction of rotation of the ferromagnetic object with a relative phase change between the first and second analog self-test signals.
6. The method of claim 1 , further comprising representing a vibration of a ferromagnetic object with a characteristic of at least one of the analog self-test signals.
7. The method of claim 6 , wherein the one or more analog self-test signals comprise a first analog self-test signal and a second analog self-test signal, wherein the characteristic comprises a relative phase change between the first and second analog self-test signals.
8. The method of claim 6 , wherein the characteristic comprises an amplitude modulation of the at least one of the one or more analog self-test signals.
9. The method of claim 1 , further comprising:
generating one or more magnetic field signals with a respective one or more magnetic field sensing elements, wherein the coupling the one or more analog self-test signals to the respective one or more offset control nodes comprises summing the analog self-test signals with respective ones of the one or more magnetic field signals.
10. The method of claim 1 , further comprising:
generating a first magnetic field signal with a first pair of magnetic field sensing elements; and
generating a second magnetic field signal with a second pair of magnetic field sensing elements, wherein the coupling the one or more analog self-test signals to the respective one or more offset control nodes comprises:
summing a first one of the one or more analog self-test signals with the first magnetic field signal; and
summing a second one of the one or more analog self-test signals with the second magnetic field signal.
11. An integrated circuit, comprising:
one or more built-in self-test signal generators for generating a respective one or more digital self-test signals;
one or more digital-to-analog converters coupled respectively to the one or more built-in self-test signal generators, the one or more digital-to-analog converters for generating a respective one or more analog self-test signals in response to the one or more digital self-test signals;
a built-in self-test control node for receiving a built-in self-test control signal; and
one or more offset control nodes coupled to receive respectively the one or more analog self-test signals in response to the built-in self-test control signal.
12. The method of claim 11 , wherein a characteristic of at least one of the analog self-test signals is representative of a proximity of a ferromagnetic object.
13. The integrated circuit of claim 11 , wherein a characteristic of at least one of the analog self-test signals is representative of a rotation of a ferromagnetic object.
14. The integrated circuit of claim 13 , wherein the one or more analog self-test signals comprise a first analog self-test signal and a second analog self-test signal, wherein a relative phase between the first and second analog self-test signals is representative of a direction of rotation of the ferromagnetic object.
15. The method of claim 14 , wherein a relative phase change between the first and second analog self-test signals is representative of a change of direction of rotation of the ferromagnetic object.
16. The integrated circuit of claim 11 , wherein a characteristic of at least one of the analog self-test signals is representative of a vibration of a ferromagnetic object.
17. The integrated circuit of claim 16 , wherein the one or more analog self-test signals comprise a first analog self-test signal and a second analog self-test signal, wherein the characteristic comprises a relative phase change between the first and second analog self-test signals.
18. The integrated circuit of claim 16 , wherein the characteristic comprises an amplitude modulation of the at least one of the one or more analog self-test signals.
19. The integrated circuit of claim 11 , further comprising one or more magnetic field sensing elements for generating a respective one or more magnetic field signals, wherein the one or more offset control nodes are further coupled to receive respectively the one or more magnetic field signals to provide respective sums of the one or more magnetic field signals with the one or more analog self-test signals.
20. The integrated circuit of claim 11 , wherein the one or more of the built-in self-test signal generators comprise:
one or more respective clock generators for generating one or more respective clock signals; and
one or more respective up/down counters coupled respectively to the one or more clock generators, the one or more up/down counters for generating the one or more digital self-test signals, wherein the one or more digital-to-analog converters are coupled respectively to receive the one or more digital self-test signals.
21. The integrated circuit of claim 20 , wherein the one or more the built-in self-test signal generators further comprise a respective one or more logic circuits coupled respectively to the one or more up/down counters for reversing a count direction.
22. The integrated circuit of claim 20 , wherein the one or more built-in self-test signal generators further comprise a respective one or more state machines coupled respectively between the one or more clock generators and the one or more up-down counters.
23. The integrated circuit of claim 11 , further comprising one or more logic circuits coupled respectively between the one or more built-in self-test signal generators and the one or more digital-to-analog converters, wherein the one or more logic circuits comprise a respective one or more logic circuit control nodes coupled to the built-in self-test control node, the one or more logic circuit control nodes for controlling coupling of the one or more analog self-test signals to the respective one or more offset control nodes.
24. The integrated circuit of claim 11 , further comprising:
a first pair of magnetic field sensing elements for generating a first magnetic field signal; and
a second pair of magnetic field sensing elements for generating a second magnetic field signal, wherein the one or more offset control nodes comprise:
a first offset control node to sum a first one of the one or more analog self-test signals with the first magnetic field signal; and
a second offset control node to sum a second one of the one or more analog self-test signals with the second magnetic field signal.
25. The integrated circuit of claim 11 , further comprising at least one of a peak detector circuit coupled to one of the one or more offset control nodes for detecting a peak of a first signal representative of a selected one of the one or more analog self-test signals or a threshold detector circuit coupled to one of the one or more offset control nodes for detecting a threshold crossing of the first signal representative of the selected one of the one or more analog self-test signals.
26. The integrated circuit of claim 25 , further comprising a vibration processor coupled to the at least one of the peak detector circuit or the threshold detector circuit for detecting at least one of a first vibration signal in the first signal representative of the selected one of the one or more analog self-test signals or a second vibration signal in a second signal representative of another selected one of the one or more analog self-test signals.