Flash memory device and fabricating method thereof
View Patent ↗A flash memory and a flash memory fabrication method for increasing the coupling ratio by HSG including forming a STI region on a silicon substrate to define an active region, forming a tunneling oxide layer on the active region, and depositing an amorphous silicon layer on the silicon substrate. The method also includes patterning the amorphous silicon layer along a bit line direction, forming an embossed silicon layer including HSGs on the patterned amorphous silicon layer, and sequentially depositing an ONO layer and a polysilicon layer for a control gate on the resulting structure. The method further includes forming a photoresist pattern on the polysilicon layer, and forming a control gate by etching the polysilicon layer using the photoresist pattern as a mask, and simultaneously forming a floating gate along the bit line.
1. A method for fabricating a flash memory device comprising the steps of:
forming a shallow trench isolation region on a silicon substrate to define an active region;
forming a tunneling oxide layer on the active region;
depositing an amorphous silicon layer on the silicon substrate;
patterning the amorphous silicon layer along a bit line direction;
forming an embossed silicon layer comprising hemisphere silicon glass on the amorphous silicon layer to enlarge a contact layer;
depositing an oxide-nitride-oxide layer on the embossed silicon layer, thereby forming a resulting structure;
depositing a polysilicon layer to form a control gate on the resulting structure;
forming a photoresist pattern on the polysilicon layer; and
forming a control gate by etching the polysilicon layer using the photoresist pattern as a mask, and simultaneously forming a floating gate along a word line direction.
2. The method as defined by claim 1 , wherein the step of forming the embossed silicon layer includes forming the embossed silicon layer on a top and sidewalls of the amorphous silicon layer.
3. A method for fabricating a flash memory device comprising:
a step for forming a shallow trench isolation region on a silicon substrate to define an active region;
a step for forming a tunneling oxide layer on the active region; a step for depositing an amorphous silicon layer on the silicon substrate; a step for patterning the amorphous silicon layer along a bit line direction;
a step for forming an embossed silicon layer comprising hemisphere silicon glass on the amorphous silicon layer to enlarge a contact layer;
a step for depositing an oxide-nitride-oxide layer on the embossed silicon layer, thereby forming a resulting structure;
a step for depositing a polysilicon layer to form a control gate on the resulting structure;
a step for forming a photoresist pattern on the polysilicon layer;
a step for forming a control gate by etching the polysilicon layer using the photoresist pattern as a mask, and simultaneously forming a floating gate along a word line direction; and
a step of forming common source and drain regions and a bit line contact.
4. The method as defined by claim 3 , wherein the step for forming an the embossed silicon layer includes a step for forming the embossed silicon layer on a top and sidewalls of the amorphous silicon layer.