Nonvolatile ferroelectric memory device
A nonvolatile ferroelectric memory device includes a plurality of memory cells connected serially between a bit line and a sensing line, a first switching unit configured to selectively connect the memory cells to the bit line in response to a first selecting signal, and a second switching unit configured to selectively connect the memory cells to the sensing line in response to a second selecting signal. The first switching unit and the second switching unit have the same structure as that of the memory cell.
1. A nonvolatile ferroelectric memory device comprising:
a plurality of memory cells connected serially between a bit line and a sensing line;
a first switching unit configured to selectively connect the plurality of memory cells to the bit line in response to a first selecting signal; and
a second switching unit configured to selectively connect the plurality of memory cells to the sensing line in response to a second selecting signal,
wherein each of the plurality of memory cells, the first switching unit, and the second switching unit comprises:
a bottom word line;
an insulating layer formed on the bottom word line;
a floating channel layer formed on the insulating layer;
a ferroelectric layer formed on the floating channel layer; and
a top word line formed on the ferroelectric layer in parallel with the bottom word line,
wherein, when a bit of “1” is written in a selected one of the memory cells, the first switching unit and the second switching unit are turned on and a negative polarization transition threshold voltage is applied to the top word line of the selected memory cell.
2. The memory device of claim 1 , wherein the floating channel layer comprises one of a carbon nano tube, a silicon, a germanium, and an organic semiconductor.
3. The memory device of claim 1 , wherein a channel resistance of the floating channel layer changes with a polarity of the ferroelectric layer.
4. The memory device of claim 1 , wherein the floating channel layer comprises:
a p-type channel region formed on the insulating layer having two sides; and
a p-type drain region and a p-type source region connected to the two sides of the p-type channel region.
5. The memory device of claim 4 , wherein the p-type channel region has a first resistance when positive charges are induced therein by a first polarization of the ferroelectric layer, and has a second resistance when negative charges are induced therein by a second polarization of the ferroelectric layer, the first resistance being lower than the second resistance.
6. The memory device of claim 1 , wherein, when a bit of “0” is written in a selected one of the memory cells, the first switching unit is turned on, the second switching unit is turned off, and a positive polarization transition threshold voltage is applied to the top word line of the selected memory cell.
7. The memory device of claim 6 , further comprising additional selected memory cells corresponding to additional bit lines, wherein, when a bit of “0” is written in the selected memory cell, a voltage having a potential equal to a half of that of the positive polarization transition threshold voltage is applied to the additional bit lines corresponding to the additional selected memory cells.
8. The memory device of claim 1 , wherein, when reading a selected one of the memory cells, the first switching unit and the second switching unit are turned on and a positive sensing voltage is applied to the bit line while a positive read voltage is applied to the bottom word line of the selected memory cell.
9. The memory device of claim 8 , wherein a current through the bit line is detected to determine a bit of datum stored in the selected memory cell.
10. A nonvolatile ferroelectric memory device comprising:
a plurality of bit lines;
a plurality of sensing lines;
a plurality of unit cell arrays each connected in common to a corresponding one of the bit lines in a column direction and to a corresponding one of the sensing lines in a row direction; and
a plurality of sense amplifiers connected to the plurality of bit line,
wherein each of the plurality of unit cell arrays comprises:
a plurality of memory cells connected serially between the corresponding bit line and the corresponding sensing line;
a first switching unit configured to selectively connect the memory cells to the corresponding bit line in response to a first selecting signal; and
a second switching unit configured to selectively connect the memory cells to the corresponding sensing line in response to a second selecting signal,
wherein each of the plurality of memory cells, the first switching unit, and the second switching unit comprises:
a bottom word line;
an insulating layer formed on the bottom word line;
a floating channel layer formed on the insulating layer;
a ferroelectric layer formed on the floating channel layer; and
a top word line formed on the ferroelectric layer in parallel with the bottom word line, and
wherein, when a bit of “1” is written in a selected one of the memory cells, the corresponding first switching unit and the corresponding second switching unit are turned on and a negative polarization transition threshold voltage is applied to the top word line of the selected memory cell.
11. The memory device of claim 10 , wherein the floating channel layer comprises:
a p-type channel region formed on the insulating layer having two sides; and
a p-type drain region and a p-type source region connected to both sides of the p-type channel region.
12. The memory device of claim 10 , wherein a channel resistance of the floating channel layer changes with a polarity of the ferroelectric layer.
13. The memory device of claim 12 , wherein the p-type channel region has a first resistance when positive charges are induced therein by a first polarization of the ferroelectric layer and has a second resistance when negative charges are induced therein by a second polarization of the ferroelectric layer, the first resistance being lower than the second resistance.
14. The memory device of claim 10 , wherein, when a bit of “0” is written in a selected one of the memory cells, the corresponding first switching unit is turned on, the corresponding second switching unit is turned off, and a positive polarization transition threshold voltage is applied to the top word line of the selected memory cell.
15. The memory device of claim 10 , further comprising additional selected memory cells associated with additional bit lines, wherein, when a bit of “0” is written in a selected one of the memory cells, a voltage having a potential equal to a half of that of a positive polarization transition threshold voltage is applied to the additional bit lines corresponding to the additional selected memory cells.
16. The memory device of claim 10 , wherein, when data stored in the selected memory cell are read, the first switching unit and the second switching unit are turned on, a positive sensing voltage is applied to the bit line, and a positive read voltage is applied to the bottom word line of the selected memory cell.
17. The memory device of claim 10 , wherein a current through the bit line is detected to read a datum stored in the selected memory cell.