IP Library Granted Patent US 7,723,129
Granted Patent B2
US 7,723,129 · App. 12/418,117 · Granted May 25, 2010

Power semiconductor devices having integrated inductor

Assignee: Texas Instruments Incorporated
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Quick Facts
Patent No.
US 7,723,129
App. No.
12/418,117
Granted
May 25, 2010
Kind
B2
Abstract

An electronic device ( 100 ) with one or more semiconductor chips ( 102 ) has an inductor ( 101 ) assembled on or under the chips. The inductor includes a ferromagnetic body ( 111 ) and a wire ( 104 ) wrapped around the body to form at least a portion of a loop; the wire ends ( 104 a ) are connected to the chips. The assembly is attached to a substrate ( 103 ), which may be a leadframe. The device may be encapsulated in molding compound ( 140 ) so that the inductor can double as a heat spreader ( 111 c ), enhancing the thermal device characteristics.

Claims (37)

1. A method for fabricating an electronic device comprising the steps of:

providing a semiconductor chip having an area, an active surface including a first and a second set of terminals, and a passive surface;

providing a substrate having contact pads;

attaching the passive chip surface to the substrate;

providing a body containing ferromagnetic material including a flat area smaller than the chip area;

attaching the flat body area to the active chip surface;

providing a bonder wire having a first and a second end;

wrapping the bonder wire around the body by means of a semiconductor wire bonder to form at least a portion of a loop;

connecting the first and second bonder wire ends to the first set terminals;

connecting the second set terminals to the contact pads; and

encapsulating the assembled chip, ferromagnetic body and electrical connections in an insulating compound.

2. A method for fabricating an electronic device comprising the steps of:

providing a semiconductor chip having an active surface including a first and a second set of terminals, and a passive surface;

providing a substrate having contact pads;

providing a body containing ferromagnetic material including a first and a second flat portion, a flat portion having connection ports;

attaching the passive chip surface to the first flat portion of the body;

providing a bonder wire having a first and a second end;

wrapping the wire around the body by means of a semiconductor wire bonder to form at least a portion of a loop;

connecting the first and second bonder wire ends to the first set terminals;

attaching the second flat portion of the body to the substrate;

connecting the first set terminals to the ports;

connecting the second set terminals to the contact pads; and

encapsulating the assembled chip, ferromagnetic body, and electrical connections in an insulating compound.

3. A method for fabricating an electronic device comprising the steps of:

attaching a first surface of a semiconductor chip to a first flat portion of a body containing ferromagnetic material;

wire-bonding a first bonder wire by means of a first semiconductor wire bonder to a first bond pad on the semiconductor chip;

wrapping a second bonder wire by means of a second semiconductor wire bonder around the body to form at least a portion of a loop; and

terminating a first end and a second end of the second bonder wire between a second bond pad and a third bond pad.

4. The method of claim 3 , in which the first bond pad, the second bond pad and the third bond pad are on the first surface of the semiconductor chip.

5. The method of claim 3 , further comprising attaching a second surface of the semiconductor chip opposite the first surface to a substrate.

6. The method of claim 3 , in which an end of the first bonder wire is bonded to a fourth bond pad on the substrate.

7. The method of claim 3 , in which the at least a portion of a loop includes multiple loops.

8. The method of claim 5 , in which the second bond pad and the third bond pad are on the substrate.

9. The method of claim 5 , in which the second bond pad and the third bond pad are on a second substrate.

10. The method of claim 5 , in which the substrate is a leadframe.

11. The method of claim 3 , in which the first and the second semiconductor wire bonder are the same wire bonder.

12. The method of claim 6 , in which the second and the third bond pad are on opposite sides of the substrate.

Continuity (2)
Division 1145841700 · Jul 19, 2006
Related Publication 20090186453A1 · Jul 23, 2009