Methods and apparatus for generating system management interrupts

1. A method comprising:

determining, using a monarch processor of a plurality of processors of a system, during initialization of the system a plurality of memory addresses, each memory address being different from one another and corresponding to a relocation address of the corresponding processor at which it is to execute system management interrupt handler code;

generating, using the monarch processor, a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor of the plurality of processors in the system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses;

directing each system management interrupt interprocessor interrupt to the corresponding processor from the monarch processor; and

verifying with a processor having a system management interrupt interprocessor interrupt directed thereto that an associated interrupt control register of the processor is set to a default address, and loading the associated interrupt control register set to the default address with the memory address included in the system management interrupt interprocessor interrupt directed to the associated processor, and otherwise not loading the interrupt control register with the memory address, and instead ignoring the memory address.

2. The method of claim 1 further comprising, executing the system management interrupt handler code with each corresponding processor, each corresponding processor executing system management interrupt code beginning at the memory address contained in the system management interrupt interprocessor interrupt directed thereto.

3. The method of claim 1 further comprising loading one of the plurality of memory addresses into an interrupt control register of the monarch processor.

4. The method of claim 1 , further comprising selecting the monarch processor as the monarch processor during initialization of the system.

5. A system comprising:

a memory device having system management interrupt handler code stored therein;

a first processor coupled to the memory device to determine during initialization a plurality of memory addresses different from one another and to generate a number of system management interrupts, each interrupt containing one of the plurality of memory addresses; and

a plurality of other processors, each coupled to the first processor and to the memory device, each to receive one of the plurality of system management interrupts as an interprocessor interrupt and to execute system management handler code beginning at the memory address contained in the system management interrupt received thereby, wherein each of the plurality of other processors comprises an interrupt control register to load the memory address contained in the received system management interrupt and is to execute software to verify that the interrupt control register is set at a default memory address prior to loading the memory address contained in the received system management interrupt, and if the interrupt control register is not set at the default memory address, to not load the memory address.

6. The system of claim 5 , wherein each of the plurality of other processors comprises an interrupt controller to receive one of the plurality of system management interrupts.

7. The system of claim 5 , wherein the first processor comprises an interrupt control register, wherein the first processor is to load one of the plurality of memory addresses into the interrupt control register.

8. A machine readable medium comprising a plurality of instructions, that in response to being executed, result in a computing device:

determining, using a monarch processor of a plurality of processors of the computing device, during initialization of the computing device a plurality of memory addresses, each memory address being different from one another and corresponding to a relocation address of the corresponding processor at which it is to execute system management interrupt handler code;

generating, using the monarch processor, a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor of the plurality of processors in the computing device and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses;

directing each system management interrupt interprocessor interrupt to the corresponding processor from the monarch processor; and

verifying with a processor having a system management interrupt interprocessor interrupt directed thereto that an associated interrupt control register of the processor is set to a default address, and loading the associated interrupt control register set to the default address with the memory address included in the system management interrupt interprocessor interrupt directed to the associated processor, and otherwise not loading the interrupt control register with the memory address, and instead ignoring the memory address.

9. The machine readable medium of claim 8 , wherein the plurality of instructions further result in the computing device executing the system management interrupt handler code with each corresponding processor, each corresponding processor executing system management interrupt code beginning at the memory address contained in the system management interrupt directed thereto.

10. The machine readable medium of claim 8 , wherein the plurality of instructions further result in the computing device loading one of the plurality of memory addresses into an interrupt control register of the monarch processor.

11. The machine readable medium of claim 8 , wherein the plurality of instructions further result in the computing device selecting the monarch processor as the monarch processor during initialization of the computing device.