IP Library Granted Patent US 7,730,435
Granted Patent B2
US 7,730,435 · App. 11/799,238 · Granted Jun 1, 2010

Automatic test component generation and inclusion into simulation testbench

Assignee: Altera Corporation
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Quick Facts
Patent No.
US 7,730,435
App. No.
11/799,238
Granted
Jun 1, 2010
Kind
B2
Abstract

Methods and apparatus are provided for efficiently generating test components for testing and evaluating a design under test. As a design is being configured, generated test components are made available. In one example, test components are automatically generated and included in a simulation testbench based on selected components in the design. Generally, the test components complement the selected components in the design. Moreover, the test components can be automatically seeded with initial contents.

Claims (27)

1. A computerized method for evaluating a device's design under test having an on-device component, the method comprising:

selecting an on-device component for inclusion in the design under test;

profiling the on-device component;

automatically generating a hardware descriptor language file corresponding to a test component module that includes a representation of an off-device component, the hardware descriptor language file generated using profile information about the on-device component, the off-device component being functionally complementary to that of the on-device component; and

inserting the test component module into a simulation testbench for evaluating the device's design under test.

2. The computerized method of claim 1 , further comprising:

generating a design under test module that includes a representation of the on-device component; and

coupling the design under test module to the test component module.

3. The computerized method of claim 2 , further comprising:

generating signals between the design under test module and the test component module to allow substantial evaluation of the device's design under test.

4. The computerized method of claim 2 , further comprising:

seeding the test component module with initial contents.

5. The computerized method of claim 2 , wherein generating the design under test module comprises:

receiving a profile for the design under test; and

using the profile to construct the design under test module.

6. The computerized method of claim 5 , wherein the profile corresponds to a parameterization of the design under test by a user.

7. The computerized method of claim 6 , wherein the parameterization comprises:

defining interfaces, data widths, and the type of signal for input and output lines associated with the design under test.

8. The computerized method of claim 1 , wherein generating the test component module comprises:

receiving a profile for the design under test; and

using the profile to construct the test component module.

9. The computerized method of claim 1 , wherein the on-device component is selected from the group consisting of adders, phase lock loops, memory, video controllers, memory controllers, processors, and timers.

10. A system for evaluating a device's design under test having an on-device component, the system comprising:

means for selecting an on-device component for inclusion in the design under test;

means for profiling the on-device component;

means for automatically generating a hardware descriptor language file corresponding to a test component module that includes a representation of an off-device component, the hardware descriptor language file generated using profile information about the on-device component, the off-device component being functionally complementary to that of the on-device component; and

means for inserting the test component module into a simulation testbench for evaluating the device's design under test.

Continuity (2)
Division 1086917400 · Jun 15, 2004
Related Publication 20070234247A1 · Oct 4, 2007