IP Library Granted Patent US 7,772,693
Granted Patent B2
US 7,772,693 · App. 11/677,774 · Granted Aug 10, 2010

Panel, semiconductor device and method for the production thereof

Assignee: Infineon Technologies AG
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Quick Facts
Patent No.
US 7,772,693
App. No.
11/677,774
Granted
Aug 10, 2010
Kind
B2
Abstract

A panel has a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components. The vertical semiconductor components in each case have a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode. The second side of the semiconductor components is in each case mounted on the metallic layer of the baseplate. The semiconductor components are arranged in such a way that edge sides of adjacent semiconductor components are separated from one another. A second metallic layer is arranged in separating regions between the semiconductor components.

Claims (45)

1. A panel, comprising:

a baseplate with an upper first metallic layer; and

a multiplicity of semiconductor components, wherein the semiconductor components in each case comprise a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode,

wherein the second side of the semiconductor components is in each case mounted on the metallic layer of the baseplate and the semiconductor components are arranged in such a way that edge sides of adjacent semiconductor components are separated from one another, and wherein a second metallic layer is arranged in separating regions between the semiconductor components,

wherein at least regions of the surface of the second metallic layer are essentially coplanar with the first load electrode and the control electrode, and

wherein said regions are arranged at four opposite edge sides of the respective semiconductor components.

2. The panel as claimed in claim 1 , wherein the second metallic layer extends between edge sides of adjacent semiconductor components.

3. The panel as claimed in claim 1 , wherein the separating regions between adjacent semiconductor components are essentially filled by the second metallic layer.

4. The panel as claimed in claim 1 , wherein the second load electrode of the semiconductor components is mounted on the metallic layer of the plate by means of a soft solder connection or a diffusion solder connection.

5. The panel as claimed in claim 1 , wherein the semiconductor components are in each case a MOSFET or an IGBT or a BJT.

6. The panel as claimed in claim 1 , wherein the baseplate of the rewiring element is a metal plate.

7. The panel as claimed in claim 1 , wherein the baseplate of the rewiring element is formed from an electrically insulating substrate with a metallic coating.

8. The panel as claimed in claim 7 , wherein the metallic coating is arranged on two sides of the electrically insulating substrate.

9. The panel as claimed in claim 7 , wherein the metallic coating is arranged only on one side of the electrically insulating substrate.

10. The panel as claimed in claim 7 , wherein the baseplate is a ceramic substrate with a DCB layer.

11. A panel, comprising:

a baseplate comprising a first metallic layer; and

a plurality of semiconductor components, wherein each of the semiconductor components comprises a first side on which a first load electrode and a control electrode are disposed, and an opposite second side on which a second load electrode is disposed,

wherein the second side of each of the semiconductor components is disposed on the first metallic layer and the semiconductor components are arranged in such a way that edge sides of adjacent ones of the semiconductor components are separated from one another, and wherein a second metallic layer is arranged in between the adjacent ones of the semiconductor components,

wherein a plurality of portions of the surface of the second metallic layer are each essentially coplanar with the first load electrode and the control electrode, and

wherein said portions of the surface of the second metallic layer are arranged at four opposite edge sides of the respective semiconductor components.

12. The panel as claimed in claim 11 , wherein the second metallic layer extends between edge sides of adjacent semiconductor components.

13. The panel as claimed in claim 11 , wherein regions between adjacent semiconductor components are essentially filled by the second metallic layer.

14. The panel as claimed in claim 11 , wherein the second load electrode of the semiconductor components is mounted on the metallic layer of the plate by means of a soft solder connection or a diffusion solder connection.

15. The panel as claimed in claim 11 , wherein the semiconductor components are in each case a MOSFET or an IGBT or a BJT.

16. The panel as claimed in claim 11 , wherein the baseplate of the rewiring element is a metal plate.

17. The panel as claimed in claim 11 , wherein the baseplate of the rewiring element comprises an electrically insulating substrate with a metallic coating.

18. The panel as claimed in claim 17 , wherein the metallic coating is arranged on two sides of the electrically insulating substrate.

19. The panel as claimed in claim 17 , wherein the metallic coating is arranged only on one side of the electrically insulating substrate.

20. The panel as claimed in claim 17 , wherein the baseplate is a ceramic substrate with a DCB layer.

21. A panel, comprising:

a baseplate comprising a first metallic layer; and

a plurality of semiconductor components, wherein each of the semiconductor components comprises a first side on which a first load electrode and a control electrode are disposed, and an opposite second side on which a second load electrode is disposed,

wherein the second side of each of the semiconductor components is disposed on the first metallic layer, edge sides of adjacent ones of the semiconductor components are separated from one another, and a second metallic layer is arranged in between the adjacent ones of the semiconductor components,

wherein a plurality of portions of the surface of the second metallic layer are each coplanar with the first load electrode and the control electrode, and

wherein said portions of the surface of the second metallic layer are arranged at four opposite edge sides of the respective semiconductor components.

22. The panel as claimed in claim 21 , wherein the second metallic layer extends between edge sides of adjacent semiconductor components.

23. The panel as claimed in claim 21 , wherein regions between adjacent semiconductor components are essentially filled by the second metallic layer.

24. The panel as claimed in claim 21 , wherein the second load electrode of the semiconductor components is mounted on the metallic layer of the plate by means of a soft solder connection or a diffusion solder connection.

25. The panel as claimed in claim 21 , wherein the semiconductor components are in each case a MOSFET or an IGBT or a BJT.

26. The panel as claimed in claim 21 , wherein the baseplate of the rewiring element is a metal plate.

27. The panel as claimed in claim 21 , wherein the baseplate of the rewiring element comprises an electrically insulating substrate with a metallic coating.

28. The panel as claimed in claim 27 , wherein the metallic coating is arranged on two sides of the electrically insulating substrate.

29. The panel as claimed in claim 27 , wherein the metallic coating is arranged only on one side of the electrically insulating substrate.

30. The panel as claimed in claim 27 , wherein the baseplate is a ceramic substrate with a DCB layer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE INVENTOR, REINHARD PLOSS'S SIGNATURE PREVIOUSLY RECORDED ON REEL 020580 FRAME 0327. ASSIGNOR(S) HEREBY CONFIRMS THE DATE OF SIGNATURE SHOULD BE MARCH 29, 2007. Recorded Jun 9, 2008
From: KOLLER, ADOLF; THEUSS, HORST; OTREMBA, RALF; HOEGLAUER, JOSEF; STRACK, HELMUT; PLOSS, REINHARD
To: INFINEON TECHNOLOGIES AG
Reel/Frame 021063/0639 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 29, 2008
From: KOLLER, ADOLF; THEUSS, HORST; OTREMBA, RALF; HOEGLAUER, JOSEF; STRACK, HELMUT; PLOSS, REINHARD
To: INFINEON TECHNOLOGIES AG
Reel/Frame 020580/0327 →
Priority Claims (1)
DE 10 2007 007 142 · Feb 9, 2007 · national
Continuity (1)
Related Publication 20080191359A1 · Aug 14, 2008