N-state ripple adder scheme coding with corresponding n-state ripple adder scheme decoding
View Patent ↗Methods and apparatus for implementing an n-state ripple-adder scheme coder with n≧2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.
1. A method of coding with a computing device a first plurality of p n-state symbols with p and n≧2 into a codeword of p n-state symbols comprising:
inputting the first plurality of p n-state symbols on the computing device;
inputting a second plurality of n-state symbols on the computing device;
processing each of p corresponding n-state symbols in the first and the second plurality of p n-state symbols with a first n-state function to generate a third plurality of p n-state symbols;
processing at least one set of corresponding n-state symbols in the first and the second plurality of p n-state symbols with a second n-state function to generate one or more n-state transfer symbols;
processing the third plurality of n-state symbols and the one or more n-state transfer symbols with a third n-state logic function; and
generating on an output of the computing device the codeword of p n-state symbols.
2. The method of claim 1 , wherein the first and the second n-state logic function are not a modulo-n adder and a corresponding modulo-n carry function.
3. The method of claim 1 , wherein the first n-state logic function is a reversible logic function.
4. The method of claim 3 , wherein the first and the third n-state logic function are the same n-state logic function.
5. The method of claim 1 , wherein the second n-state logic function is a non-reversible logic function.
6. The method of claim 1 , further comprising processing a complete ripple of n-state transfer symbols through the first plurality of n-state symbols.
7. The method of claim 1 , wherein the codeword is generated in a Feistel network.
8. The method of claim 1 , wherein an n-state symbol is represented by one or more binary signals.
9. The method of claim 1 , wherein an n-state logic function is implemented with binary circuitry.
10. The method of claim 1 , wherein the computing device is part of a communication system.
11. The method of claim 1 , wherein the computing device is part of a financial system.
12. The method of claim 1 , further comprising a corresponding method to retrieve from the codeword the first plurality of p n-state symbols.
13. An apparatus for coding a first plurality of p n-state symbols with p and n≧2 into a codeword of p n-state symbols comprising:
a processor with memory, the memory enabled to store instructions, the processor retrieving the instructions from the memory and executing the instruction on signals representing n-state symbols to perform the steps of:
receiving signals representing the first plurality of p n-state symbols on a first input;
receiving signals representing a second plurality of n-state symbols on a second input;
processing signals representing each of p corresponding n-state symbols in the first and the second plurality of p n-state symbols with a first n-state function to generate signals representing a third plurality of p n-state symbols;
processing signals representing at least one set of corresponding n-state symbols in the first and the second plurality of p n-state symbols with a second n-state function to generate one or more n-state transfer symbols;
processing the signals representing the third plurality of n-state symbols and the one or more n-state transfer symbols with a third n-state logic function; and
generating signals representing the codeword of p n-state symbols.
14. The apparatus of claim 13 , wherein the first and the second n-state logic function are not a modulo-n adder and a corresponding modulo-n carry function.
15. The apparatus of claim 13 , wherein the first n-state logic function is a reversible logic function.
16. The apparatus of claim 15 , wherein the first and the third n-state logic function are the same n-state logic function.
17. The apparatus of claim 13 , further comprising processing a complete ripple of n-state transfer symbols through the first plurality of n-state symbols.
18. The apparatus of claim 17 , further comprising an apparatus to determine from the signals representing the codeword the signals representing the first plurality of p n-state symbols.
19. The apparatus of claim 13 , wherein the codeword is generated in a Feistel network.
20. The apparatus of claim 13 , wherein an n-state symbol is represented by one or more binary signals.
21. The apparatus of claim 13 , wherein an n-state logic function is implemented with binary circuitry.
22. The apparatus of claim 13 , wherein the apparatus is part of a financial system.