IP Library Granted Patent US 7,774,725
Granted Patent B1
US 7,774,725 · App. 11/593,465 · Granted Aug 10, 2010

Computationally efficient modeling and simulation of large scale systems

Assignee: Purdue Research Foundation
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Quick Facts
Patent No.
US 7,774,725
App. No.
11/593,465
Granted
Aug 10, 2010
Kind
B1
Abstract

A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X 1 and at least one other matrix, with first equation including X 1 Y, X 1 A, and X 1 P, and the second equation including X 1 A and X 1 P.

Claims (112)

1. A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, comprising:

obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for said interconnect structure, said element values for each matrix including inductance L and inverse capacitance P;

obtaining an adjacency matrix A associated with said interconnect structure;

using a processor to perform numerical integration to solve first and second equations each including as a factor the product of the inverse matrix X −1 and at least one other matrix, said first equation including X −1 Y, X −1 A, and X −1 P, and said second equation including X −1 A and X −1 P.

2. The method of claim 1 , wherein matrices X and Y each contain resistance values R in addition to L and P.

3. The method of claim 2 , wherein said first equation is substantially of the form

i

l

k

+

1

=

X

-

1

Yi

l

k

+

X

-

1

Av

n

k

+

h

4

X

-

1

AP

(

I

s

k

+

1

+

I

s

k

)

,

where v n and i l are node voltages and inductor currents, respectively, A is an adjacency matrix for the circuit, and I s is a current source vector, and

wherein said second equation is substantially of the form

X

-

1

Av

n

k

+

1

=

X

-

1

Av

n

k

-

h

2

X

-

1

APA

T

(

i

l

k

+

1

+

i

l

k

)

+

h

2

X

-

1

AP

(

I

s

k

+

1

+

I

s

k

)

.

Assignments (1)
CONFIRMATORY LICENSE Recorded May 18, 2010
From: PURDUE UNIVERSITY
To: NATIONAL SCIENCE FOUNDATION
Reel/Frame 024400/0635 →
Continuity (2)
Provisional Application 6073346000 · Nov 4, 2005
Provisional Application 6074099000 · Nov 30, 2005