Display device
The present invention provides a display device having thin film transistors which can reduce an OFF current in spite of the extremely simple constitution. In the display device having thin film transistors on a substrate, each thin film transistor includes a gate electrode which is connected with a gate signal line, a semiconductor layer which is formed astride the gate electrode by way of an insulation film, a drain electrode which is connected with a drain signal line and is formed on the semiconductor layer, and a source electrode which is formed on the semiconductor layer in a state that the source electrode faces the drain electrode in an opposed manner, and a side of the drain electrode which faces the source electrode does not overlap the gate electrode as viewed in a plan view, and a side of the source electrode which faces the drain electrode does not overlap the gate electrode as viewed in a plan view.
1. A display device comprising:
a substrate;
thin film transistors which are formed on the substrate;
gate signal lines;
gate electrodes which are connected to the gate signal lines;
semiconductor layers each of which is formed across the gate electrodes by way of an insulation film, each semiconductor layer being formed into a polysilicon layer by radiation of laser beams;
a contact layer having a high impurity concentration and being formed above the semiconductor layers;
drain signal lines;
drain electrodes each of which is connected with the drain signal lines and is formed on the semiconductor layers by way of the contact layer; and
source electrodes each of which is formed on the semiconductor layers by way of the contact layer in a state that a side of the source electrodes faces a side of the drain electrodes in an opposed manner, wherein
a first side of the contact layer is formed between the semiconductor layers and the drain electrodes and does not overlap the gate electrodes as viewed in a plan view, and
a first side of the contact layer is formed between the semiconductor layers and the source electrodes and does not overlap the gate electrodes as viewed in a plan view.
2. A display device according to claim 1 , wherein the side of the drain electrode which faces the source electrode is spaced apart from the gate electrode by a value which falls within a range from 0 to 5 μm as viewed in a plan view, and the side of the source electrode which faces the drain electrode is spaced apart from the gate electrode by a value which falls within a range from 0 to 5 μm as viewed in a plan view.
3. A display device according to claim 1 , wherein the side of the drain electrode which faces the source electrode is spaced apart from the gate electrode by a value which falls within a range from 2 to 5 μm as viewed in a plan view, and the side of the source electrode which faces the drain electrode is spaced apart from the gate electrode by a value which falls within a range from 2 to 5 μm as viewed in a plan view.
4. A display device according to claim 1 , wherein the semiconductor layer is made of poly-silicon.
5. A display device according to claim 1 , wherein a display region in which a plurality of pixels is arranged and a peripheral region which surrounds the display region are formed on the substrate, and the thin film transistor is formed in each pixel.
6. A display device according to claim 1 , wherein a display region in which a plurality of pixels is arranged and a peripheral region which surrounds the display region are formed on the substrate, and the thin film transistors are formed in the peripheral region.
7. A display device comprising:
thin film transistors;
drain signal lines;
drain electrodes each of which is connected with the drain signal lines;
source electrodes, a side of the source electrodes facing a side of the drain electrodes;
semiconductor layers each of which is arranged below the drain electrodes and the source electrodes in an overlapping manner and is formed into a poly-silicon layer by radiation of laser beams;
a contact layer having a high impurity concentration and being formed between the semiconductor layers and the source and drain electrodes; and
gate electrodes which are formed below the semiconductor layers by way of an insulation layer, wherein
a first side of the contact layer is formed between the semiconductor layers and the drain electrodes and does not overlap the gate electrodes as viewed in a plan view, and
a first side of the contact layer is formed between the semiconductor layers and the source electrodes and does not overlap the gate electrodes as viewed in a plan view.
8. A display device according to claim 7 , wherein the side of the drain electrode which faces the source electrode is spaced apart from the gate electrode by a value which falls within a range from 0 to 5 μM as viewed in a plan view, and the side of the source electrode which faces the drain electrode is spaced apart from the gate electrode by a value which falls within a range from 0 to 5 μm as viewed in a plan view.
9. A display device according to claim 7 , wherein the side of the drain electrode which faces the source electrode is spaced apart from the gate electrode by a value which falls within a range from 2 to 5 μm as viewed in a plan view, and the side of the source electrode which faces the drain electrode is spaced apart from the gate electrode by a value which falls within a range from 2 to 5 μm as viewed in a plan view.
10. A display device according to claim 7 , wherein the semiconductor layer is made of poly-silicon.
11. A display device according to claim 7 , wherein a display region in which a plurality of pixels is arranged and a peripheral region which surrounds the display region are formed on the substrate, and the thin film transistor is formed in each pixel.
12. A display device according to claim 7 , wherein a display region in which a plurality of pixels is arranged and a peripheral region which surrounds the display region are formed on the substrate, and the thin film transistors are formed in the peripheral region.