Apparatus of low power, area efficient FinFET circuits and method for implementing the same
View Patent ↗A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area.
1. A majority gate having three inputs and an output comprising:
a first N-FinFET having a source, a drain, a front gate, and a back gate; the drain of the first N-FinFET is connected to the output of the majority gate;
a second N-FinFET having a source, a drain, a front gate, and a back gate, the drain of the second N-FinFET is connected to the source of the first N-FinFET;
a third N-FinFET having a source, a drain, a front gate, and a back gate, the drain of the third N-FinFET is connected to the source of the second N-FinFET, the source of the third N-FinFET is connected to a low reference voltage
a first P-FinFET having a source, a drain, a front gate, and a back gate; the drain of the first P-FinFET is connected to the output of the majority gate;
a second P-FinFET having a source, a drain, a front gate, and a back gate, the drain of the second P-FinFET is connected to the source of the first P-FinFET;
a third P-FinFET having a source, a drain, a front gate, and a back gate, the drain of the third P-FinFET is connected to the source of the second P-FinFET, the source of the third P-FinFET is connected to a high reference voltage.
2. The six-transistor majority gate of claim 1 , wherein the first N-FinFET, the second N-FinFET, and the third N-FinFET have input pairs (A′, B′), (A′, C′) and (B′, C′) in no particular order, where A′, B′, C′ are complement of the primary inputs A, B, C of the majority gate.
3. The majority gate of claim 2 , wherein the first P-FinFET, the second P-FinFET, and the third P-FinFET have input pairs (A′, B′), (A′, C′) and (B′, C′) in no particular order.
4. A 2-1 MUX having two data inputs, a selection input, and an output, comprising:
a first N-FinFET having a source, a drain, and two gates; the drain of the first N-FinFET is connected to the output of the majority gate;
a second N-FinFET having a source, a drain, and two gates, the drain of the second N-FinFET is connected to the source of the first N-FinFET; the source of the second N-FinFET is coupled to a ground reference voltage.
a first P-FinFET having a source, a drain, and two gates; the drain of the first P-FinFET is connected to the output of the majority gate;
a second P-FinFET having a source, a drain, and two gates, the drain of the second P-FinFET is connected to the source of the first P-FinFET; the source of the second P-FinFET is coupled to a high reference voltage.
5. The 2-1 MUX of claim 4 , wherein the first N-FinFET and the second N-FinFET have input pairs (S, A′) and (S′, B′), in no particular order, where A′ and B′ are complement of the data inputs A, B, wherein S is the selection input and S′ is the complement of S.
6. The 2-1 MUX of claim 5 , wherein the first P-FinFET and the second P-FinFET have input pairs (S, B′) and (S′, A′), in no particular order.
7. A method for generating any digital circuit by first writing the output expression in OR-AND form, translate the OR-AND expression into CMOS circuit, and then merge any two parallel NMOS transistors or any two parallel PMOS transistors into one N-FinFET or one P-FinFET.
8. A computer readable storage medium for generating a digital circuit comprising an output, the computer readable storage medium carrying one or more sequences of one or more instructions which, when executed by one or more processors, cause the one or more processors to perform the computer-implemented steps of:
writing an output expression corresponding to the output of the digital circuit in OR-AND form;
translating the OR-AND expression into digital circuit having NMOS and PMOS; and
merging two parallel NMOS transistors into a N-FinFET; and
merging two parallel PMOS transistors into a P-FinFET.
9. The computer readable storage medium recited in claim 8 , wherein the one or more sequences of one or more instructions further cause the one or more processors to perform the computer-implemented steps of:
replacing an unpaired NMOS transistor with a N-FinFET; and
replacing an unpaired PMOS transistor with a P-FinFET.