Flat panel display incorporating control frame
A flat panel display including: a plurality of electrically addressable pixels; a plurality of thin-film transistor driver circuits each being electrically coupled to an associated at least one of the pixels, respectively; a passivating layer on the thin-film transistor driver circuits and at least partially around the pixels; a conductive frame on the passivating layer; and, a plurality of nanostructures on the conductive frame; wherein, exciting the conductive frame and addressing one of the pixels using the associated driver circuit causes the nanostructures to emit electrons that induce the one of the pixels to emit light.
1. A flat panel display comprising;
a plurality of electrically addressable pixels, each of said pixels being electrically addressable by including a conductive pad that is coated with a phosphor;
a plurality of thin-film transistor (TFT) driver circuits each being electrically coupled to an associated one of said plurality of said pixels;
a passivating layer on said thin-film transistor driver circuits and at least partially around said pixels;
a conductive frame on said passivating layer, wherein conductor elements of said frame are positioned between said pixels to substantially surround each of said pixels;
a plurality of nanostructures on said conductive frame;
a substrate supporting said pixels including said phosphor coated conductive pad, said TFT driver circuits, said passivating layer and said conductive frame,
means for applying a known voltage to said conductive frame, said known voltage being less than an electron emission threshold voltage of said nanostructures; and
means for addressing one of said pixels using said associated driver circuit, wherein said addressing causes application of a voltage to said pixel to create a potential difference greater than said emission threshold voltage.
2. The display of claim 1 , wherein said substrate is transparent.
3. The display of claim 1 , further comprising:
a second substrate oppositely disposed from said substrate supporting said pixels, said driver circuits, said passivating layer and said frame, wherein said second substrate is transparent.
4. The display of claim 1 , wherein said conductive frame comprises a plurality of parallel rows of conductors.
5. The display of claim 1 , wherein said conductive frame comprises a plurality of parallel columns of conductors.
6. The display of claim 1 , wherein said conductive frame comprises a matrix of row and column conductors defining a plurality of cells each associated with one of said pixels.
7. The display of claim 1 , further comprising at least one contact pad electrically coupled to said conductive frame.
8. The display of claim 1 , wherein said nanostructures comprise carbon nanotubes.
9. The display of claim 1 , wherein:
said driver circuit comprises at least one transistor coupled to said conductive pad.
10. The display of claim 1 , wherein:
said driver circuit comprises a first transistor coupled to said conductive pad and a second transistor and capacitor coupled to a gate of said first transistor.
11. A display comprising:
a substrate;
a plurality of electrically addressable pixels supported on said substrate, said electrically addressable pixels being coated with a phosphor,
a passivating layer covering said substrate;
a conductive frame supported on said passivating layer, wherein elements of said conductive frame are positioned between said pixels to substantially surround each of said pixels; and
a plurality of nanostructures on said conductive frame;
means for applying a predetermined voltage to said conductive frame, said predetermined voltage being less than an electronic emission threshold voltage of said nanostructures;
means for addressing one of said pixels to apply a voltage to selected ones of said addressable pixels to create a voltage difference greater than said electronic emission threshold voltage.
12. The display of claim 11 , wherein said substrate is transparent.
13. The display of claim 11 , further comprising:
a second substrate oppositely disposed from said substrate, wherein said second substrate is transparent.
14. The display of claim 11 , wherein said conductive frame comprises a matrix of row and column conductors defining a plurality of cells each associated with one of said pixels.
15. The display of claim 11 , further comprising at least one contact pad electrically coupled to said conductive frame.
16. The display of claim 11 , wherein said nanostructures comprise carbon nanotubes.
17. The display of claim 11 , wherein each said pixel comprises a conductive pad and at least one transistor coupled to said conductive pad.
18. The display of claim 11 , wherein each said pixel comprises a conductive pad, a first transistor coupled to said conductive pad, and a second transistor and capacitor coupled to a gate of said first transistor.