IP Library Granted Patent US 7,816,672
Granted Patent B2
US 7,816,672 · App. 11/846,092 · Granted Oct 19, 2010

Wiring pattern, electronic device, organic semiconductor device, layered wiring pattern, and layered wiring substrate using the wiring pattern

Assignee: Ricoh Company, Ltd.
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Quick Facts
Patent No.
US 7,816,672
App. No.
11/846,092
Granted
Oct 19, 2010
Kind
B2
Abstract

A wiring pattern is disclosed including: a variable wettability layer including a material whose critical surface tension changes in response to energy provided thereto, the wettability changing layer including a high surface energy part exhibiting a high critical surface tension and a low surface energy part exhibiting low critical surface tension; and a conductive pattern layer formed on the variable wettability layer at the high surface energy part. The conductive pattern layer has an elongated shape with a chamfered corner part in a plan view.

Claims (39)

1. A wiring pattern comprising:

a variable wettability layer including a material whose critical surface tension changes in response to energy provided thereto, the variable wettability layer including a high surface energy part exhibiting a high critical surface tension and a low surface energy part exhibiting a low critical surface tension; and

a conductive pattern layer formed on the variable wettability layer at the high surface energy part;

wherein the conductive pattern layer has an elongated shape with a chamfered corner part in a plan view and the high surface energy part includes a chamfered corner part in a plan view.

2. The wiring pattern as claimed in claim 1 , further comprising:

a semiconductor layer contacting the low surface energy part.

3. The wiring pattern as claimed in claim 2 , wherein the semiconductor layer is an organic semiconductor layer.

4. The wiring pattern as claimed in claim 1 , wherein another conductive pattern layer is formed on an entire surface of the wiring pattern via an insulating layer.

5. The wiring pattern as claimed in claim 4 , wherein the other conductive pattern layer is disposed on a high surface energy part of another variable wettability layer.

6. The wiring pattern as claimed in claim 1 , wherein the chamfered corner part has a rounded shape in a plan view.

7. The wiring pattern as claimed in claim 1 , wherein the conductive pattern layer is formed by using an inkjet method which applies a conductive liquid on the high surface energy part of the variable wettability layer.

8. An electronic device comprising:

the wiring pattern as claimed in claim 1 .

9. A layered wiring pattern comprising:

a plurality of layers of the wiring pattern claimed in claim 1 , wherein an insulating film is provided between each of the layers.

10. The layered wiring pattern as claimed in claim 9 , wherein the elongated conductive pattern layer of the wiring pattern does not overlap with those of the wiring pattern of other layers.

11. A layered wiring pattern substrate comprising:

a substrate on which the wiring pattern claimed in claim 1 is formed.

12. An organic semiconductor device comprising:

a wiring pattern having

a variable wettability layer including a material whose critical surface tension changes in response to energy provided thereto, the variable wettability layer including a high surface energy part exhibiting a high critical surface tension and a low surface energy part exhibiting a low critical surface tension,

a conductive pattern layer formed on the variable wettability layer at the high surface energy part, and

an organic semiconductor layer contacting the low surface energy part; and

another conductive pattern layer formed on either an entire surface of the wiring pattern via another variable wettability layer or an insulating layer formed on the organic semiconductor layer;

wherein the conductive pattern layer has an elongated shape with a chamfered corner part in a plan view and the high surface energy part includes a chamfered corner part in a plan view.

13. The organic semiconductor device as claimed in claim 12 , wherein the chamfered corner part has a rounded shape in a plan view.

14. The organic semiconductor device as claimed in claim 12 , wherein the organic semiconductor device is a thin film transistor (TFT).

15. A method for producing a wiring pattern comprising:

forming a variable wettability layer, the variable wettability layer including a material whose critical surface tension changes in response to energy provided thereto, the variable wettability layer including a high surface energy part exhibiting a high critical surface tension and a low surface energy part exhibiting a low critical surface tension;

forming a mask having a pattern for a conductive pattern layer on the variable wettability layer, wherein the mask is chamfered at a corner part in a plan view;

forming the high surface energy part having a chamfered corner part in a plan view by using the mask; and

forming the conductive pattern layer on the variable wettability layer at the high surface energy part by using an inkjet method which applies a conductive liquid on the high surface energy part of the variable wettability layer,

wherein the conductive pattern layer has an elongated shape with a chamfered corner part in a plan view.

16. The method according to claim 15 , further comprising:

forming another conductive pattern layer on an insulating layer formed on the wiring pattern.

17. The method according to claim 16 , further comprising:

forming the other conductive pattern layer by applying a conductive liquid onto a high surface energy part of another variable wettability layer.

18. The method according to claim 15 , further comprising:

providing a substrate on which the variable wettability layer is formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2007
From: TOMONO, HIDENORI; KAWASHIMA, IKUE; SUZUKI, KOEI; AKIYAMA, YOSHIKAZU
To: RICOH COMPANY, LTD.
Reel/Frame 019913/0664 →
Priority Claims (1)
JP 2006-243988 · Sep 8, 2006 · national
Continuity (1)
Related Publication 20080061288A1 · Mar 13, 2008