IP Library Granted Patent US 7,824,964
Granted Patent B2
US 7,824,964 · App. 12/412,479 · Granted Nov 2, 2010

Method for fabricating package structures for optoelectronic devices

Assignee: VisEra Technologies Company Limited
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Quick Facts
Patent No.
US 7,824,964
App. No.
12/412,479
Granted
Nov 2, 2010
Kind
B2
Abstract

A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same.

Claims (28)

1. A method for fabricating package structures for optoelectronic devices, comprising:

reversely placing a device wafer on a first substrate, wherein the device wafer comprises:

a second substrate; and

a first dielectric layer between the first and second substrates, comprising at least one pair of pads formed in the first dielectric layer;

forming a first opening in the second substrate and the first dielectric layer to expose the surface and sidewall of the pair of pads;

forming a metal layer directly on the exposed surface of each pad and covering the second substrate;

forming a protective layer on the metal layer and filling the first opening in the first dielectric layer;

forming at least one second opening in the protective layer, corresponding to each pad and exposing a portion of the metal layer on the second substrate;

forming a solder ball in the second opening, electrically connecting to the metal layer; and

dicing the device wafer and the first substrate along the first opening in the first dielectric layer.

2. The method as claimed in claim 1 , further forming a second dielectric layer between the second substrate and the metal layer.

3. The method as claimed in claim 1 , further forming a dam between the first substrate and the first dielectric layer to form a cavity therebetween.

4. The method as claimed in claim 1 , further forming a glue layer between the first substrate and the first dielectric layer.

5. The method as claimed in claim 1 , wherein the first substrate comprises glass and the second substrate comprises silicon.

6. A method for fabricating package structures for optoelectronic devices, comprising:

placing a device wafer between first and second substrates, comprising:

a third substrate adjacent to the first substrate; and

a first dielectric layer between the second and third substrates, comprising at least one pair of pads formed in the first dielectric layer;

forming a first opening in the second substrate and the first dielectric layer to expose the surface and sidewall of the pair of pads;

forming a metal layer directly on the exposed surface of each pad and covering the second substrate;

forming a protective layer on the metal layer and filling the first opening in the first dielectric layer;

forming at least one second opening in the protective layer, corresponding to each pad and exposing a portion of the metal layer on the second substrate;

forming a solder ball in the second opening, electrically connecting to the metal layer; and

dicing the device wafer and the first substrate along the first opening in the first dielectric layer.

7. The method as claimed in claim 6 , further forming a second dielectric layer between the second substrate and the metal layer.

8. The method as claimed in claim 6 , further forming a dam between the first and third substrates to form a cavity therebetween.

9. The method as claimed in claim 6 , further forming a glue layer between the first and third substrates.

10. The method as claimed in claim 6 , wherein the first substrate comprises glass and the second and third substrates comprises silicon.

Continuity (2)
Division 1165208400 · Jan 11, 2007
Related Publication 20090186449A1 · Jul 23, 2009