IP Library Granted Patent US 7,830,666
Granted Patent B2
US 7,830,666 · App. 11/831,888 · Granted Nov 9, 2010

Manufacturing process for single-chip MMC/SD flash memory device with molded asymmetric circuit board

Assignee: Super Talent Electronics, Inc.
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Quick Facts
Patent No.
US 7,830,666
App. No.
11/831,888
Granted
Nov 9, 2010
Kind
B2
Abstract

An MMC/SD core unit includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips include, for example, a controller chip and a flash memory chip, or a single-chip (combined controller/flash memory) chip. Multiple flash IC chips are optionally stacked to increase storage capacity. The IC chip(s) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. A molded housing is then formed over the IC chips and passive components such that the device has a uniform thickness. The MMC/SD core unit is then inserted or otherwise mounted in an eternal casing to provide a finished MMC/SD device.

Claims (39)

1. A MMC/SD flash memory device comprising:

a core unit including:

a printed circuit board assembly (PCBA) including:

a printed circuit board (PCB) having opposing first and second surfaces,

a plurality of metal contacts disposed on the first surface of the PCB,

at least one passive component mounted on the second surface of the PCB,

at least one unpackaged integrated circuit (IC) die mounted on the second surface of the PCB, and

a plurality of conductive traces formed on the PCB such that each conductive trace is electrically connected to at least one of an associated metal contact, said at least one IC die and said at least one passive component; and

a single-piece molded housing formed on the second surface of the PCBA such that said at least one passive component, said at least one IC die, and all remaining exposed portions of the second surface are covered by said molded housing, and such that substantially all of the first surface of the PCB is exposed; and

an external casing mounted onto the core unit such that the metal contacts are exposed,

wherein the molded housing includes a planar surface extending parallel to the PCB, and

wherein the molded housing includes a peripheral wall extending perpendicular to the planar surface, and wherein the peripheral wall is aligned with a peripheral edge of the PCB.

2. The MMC/SD flash memory device of claim 1 , wherein the at least one integrated circuit (IC) die is electrically connected to the conductive traces by a plurality of wire bonds extending between said at least one IC die and corresponding contact pads disposed on the second surface of the PCB.

3. The MMC/SD flash memory device of claim 2 , wherein the at least one passive component includes a lead that is soldered to a corresponding contact pad disposed on the second surface of the PCB.

4. The MMC/SD flash memory device of claim 3 , wherein the at least one passive component comprises at least one of a resistor and a capacitor.

5. The MMC/SD flash memory device of claim 2 , wherein the at least one integrated circuit (IC) die includes a first IC die comprising a controller circuit, and a second IC die comprising a flash memory circuit.

6. The MMC/SD flash memory device of claim 5 , wherein the at least one integrated circuit (IC) die comprises a plurality of flash memory dies disposed in a stacked arrangement such that a first flash memory die is mounted on the second surface of the PCB, and a second flash memory die is mounted on a surface of the first flash memory die.

7. The MMC/SD flash memory device of claim 6 , wherein the first flash memory die is connected to said PCB by a first plurality of said wire bonds, and the second flash memory die is connected to one of the first flash memory die and said PCB by a second plurality of wire bonds.

8. The MMC/SD flash memory device of claim 2 , wherein the at least one integrated circuit (IC) die includes a single-chip controller/flash die comprising controller circuit and one or more flash block mass storage circuits that are interconnected by a bus.

9. The MMC/SD flash memory device of claim 1 , wherein the external casing comprises a box-like structure having a flat lower wall and a peripheral wall that extends upward from the bottom wall, and wherein the core unit is inserted into the external casing such that a planar lower surface of the molded housing presses against the flat lower wall, and such that the peripheral wall of the casing extends over side walls of the molded housing.

10. The MMC/SD device of claim 9 , wherein the casing further comprises a thermal adhesive tape disposed between the planar lower surface of the molded housing and the flat lower wall of the casing.

11. The MMC/SD flash memory device of claim 1 ,

wherein the external casing comprises a box-like top cover having a flat top wall defining openings and a first peripheral wall, and a bottom cover having a flat bottom wall having a second peripheral wall, and

wherein the core unit is inserted into the external casing such that the metal contacts of are exposed through the openings defined in the flat top wall, a planar lower surface of the molded housing presses against the flat bottom wall, and such that the first and second peripheral walls extend over side walls of the molded housing.

12. The MMC/SD flash memory device of claim 11 , wherein the top cover is secured to the bottom cover by one of ultrasonic welding, an adhesive epoxy, a snap-on structure, and an over-molding process.

13. The MMC/SD flash memory device of claim 11 , wherein the external casing further comprises a plastic switch tablet that is slidably engaged in a switch cavity slot defined in the bottom cover.

14. A method for producing an MMC/SD flash memory device comprising:

producing a printed circuit board (PCB) including opposing first and second surfaces, a plurality of metal contacts disposed on the first surface, a plurality of first contact pads disposed on the second surface, a plurality of second contact pads disposed on the second surface, and a plurality of conductive traces formed on the PCB such that each conductive trace is electrically connected to at least one of an associated metal contact, a first contact pad and a second contact pad, wherein producing the PCB comprises forming a PCB panel including at least ten of said PCBs arranged in two rows;

attaching at least one passive component to the first contact pads of each of said at least ten of said PCBs using a surface mount technique;

attaching at least one unpackaged integrated circuit (IC) die to the second contact pads of each of said at least ten of said PCBs using a chip-on-board technique;

forming a single-piece molded housing on the second surface of all of said at least ten of said PCBs such that said at least one passive component and said at least one IC die of all of said at least ten of said PCBs are covered by a uniform block formed by said molded housing, and such that substantially all of the first surface of each of said at least ten of said PCBs is exposed;

singulating said PCB panel such that a portion of the molded housing remains on each of said at least ten of said PCBs, such that said molded housing portion includes a peripheral wall extending perpendicular to said each of said at least ten of said PCBs, and such that the peripheral wall is aligned with a peripheral edge of said each of said at least ten of said PCBs, thereby forming at least ten core units; and

mounting each of said at least ten core units onto an associated external casing.

15. The method of claim 14 , wherein attaching said at least one passive component comprises:

printing a solder paste on said first contact pads;

mounting said at least one component on said first contact pads; and

reflowing the solder paste such that said at least one component is fixedly soldered to said first contact pads.

16. The method of claim 14 , further comprising grinding a wafer including said at least one IC die such that a thickness of said wafer is reduced during said grinding, and then dicing said wafer to provide said at least one IC die.

17. The method of claim 16 , wherein attaching at least one IC die comprises bonding said at least one IC die to the second surface of the PCB and wire bonding the at least one IC die to said second contact pad.

Assignments (2)
CHANGE OF NAME Recorded Mar 27, 2014
From: SUPER TALENT ELECTRONIC, INC.
To: SUPER TALENT TECHNOLOGY, CORP.
Reel/Frame 032540/0565 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2007
From: HIEW, SIEW S.; NI, JIM C.; HSUEH, PAUL; LEE, CHARLES C.; SHEN, MING-SHIANG
To: SUPER TALENT ELECTRONICS INC.
Reel/Frame 019887/0240 →
Continuity (16)
Continuation In Part 1177383000 · Jul 5, 2007
Continuation In Part 1130959400 · Aug 28, 2006
Continuation In Part 1070727700 · Dec 2, 2003
Continuation In Part 1183188800
Continuation In Part 1146675900 · Aug 23, 2006
Continuation In Part 0947872000 · Jan 6, 2000
Continuation In Part 1183188800
Continuation In Part 1145898700 · Jul 20, 2006
Continuation In Part 1076185300 · Jan 20, 2004
Continuation In Part 1183188800
Continuation In Part 1078933300 · Feb 26, 2004
Continuation In Part 1162466700 · Jan 18, 2007
Continuation In Part 1091386800 · Aug 6, 2004
Continuation In Part 1183188800
Continuation In Part 1130984400 · Oct 11, 2006
Related Publication 20080006927A1 · Jan 10, 2008