Configurable IC with deskewing circuits
Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs. In some embodiments the configurable IC is a subcycle reconfigurable IC. In some such embodiments each of the deskew circuits further includes a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle. In some embodiments the multiple deskew circuits send data to trigger circuit. In some such embodiments the trigger circuit triggers a trace buffer to stop recording a data stream. In some such embodiments the trigger circuit triggers the trace buffer to stop after a programmable delay.
1. An integrated circuit (“IC”) comprising:
a trigger circuit for triggering a circular trace buffer, the trigger circuit comprising a set of inputs; and
a plurality of deskew circuits comprising a set of outputs communicatively connected to the set of inputs of said trigger circuit,
the trigger circuit for receiving data from the set of outputs of the plurality of deskew circuits through the set of inputs of the trigger circuit, and for triggering the circular trace buffer to stop recording a data stream.
2. The IC of claim 1 , wherein the circular trace buffer continuously stores the data stream until instructed otherwise.
3. An integrated circuit (“IC”) comprising:
a) a plurality of multi-input deskew circuits comprising a set of outputs;
b) a trigger circuit for triggering a trace buffer, wherein said set of outputs of said plurality of multi-input deskew circuits are communicatively connected to a set of inputs of said trigger circuit; and
c) a multi-layered transport network for transporting data to said plurality of multi-input deskew circuits.
4. The IC of claim 3 , wherein data lines from a first layer of said multi-layered transport network connect to at least one of the deskew circuits in said plurality of multi-input deskew circuits.
5. The IC of claim 3 , wherein data lines from a second layer of said multi-layered transport network connect to at least one of the deskew circuits in said plurality of multi-input deskew circuits.
6. The IC of claim 5 , wherein the data lines from the first layer of said multi-layered transport network connect to all of said plurality of multi-input deskew circuits.
7. An integrated circuit (“IC”) comprising:
a) a plurality of deskew circuits comprising a set of outputs; and
b) a trigger circuit for triggering a trace buffer to stop recording a data stream after a programmable delay, wherein said set of outputs of said plurality of deskew circuits are communicatively connected to a set of inputs of said trigger circuit.
8. The IC of claim 7 , wherein said trace buffer is a circular trace buffer.
9. The IC of claim 8 , wherein:
a) said IC is a subcycle reconfigurable IC; and
b) said circular trace buffer is for recording for N subcycles, wherein N is a number.
10. The IC of claim 9 , wherein said delay is about half of N subcycles.
11. For an integrated circuit with a trace buffer, and trigger circuits for triggering said trace buffer to stop recording, a method comprising:
temporally aligning a set of data bits into a temporally aligned set of data bits, wherein said temporally aligning is by a set of deskew circuits, wherein at least one of the deskew circuits in said set of deskew circuits is a multi-input deskew circuit;
passing said temporally aligned set of data bits to said trigger circuits and
recording said set of data bits at said trace buffer.
12. The method of claim 11 , wherein the multi-input deskew circuit receives data from every output of a transport network.
13. The method of claim 12 , wherein the multi-input deskew circuit communicatively connects only one output of the transport network to said trigger circuit.