Hybrid hardware and software implementation of transactional memory access

1. A method comprising:

selecting, from among modes having a hardware mode and a software mode, the hardware mode to implement transactional memory accesses including detecting an orphan transaction, the orphan transaction including an uncommitted transaction capable of corrupting a memory or a corresponding software program, the hardware mode to utilize a transaction cache of a processor, the software mode to utilize a regular cache of the processor; and

invoking, via the hardware mode utilizing the transaction cache, an orphan transaction exception in lieu of a transaction validate instruction to asynchronously notify a thread of the detection of the orphan transaction, the notification to prevent the orphan transaction from corrupting the memory or the corresponding software program.

2. The method of claim 1 , further comprising:

selecting the software mode if an abort instruction is issued in the hardware mode; and

invoking the orphan transaction exception in lieu of the transaction validate instruction via the software mode if the abort instruction is issued in the hardware mode.

3. The method of claim 2 , further comprising issuing an abort instruction if a conflicting transaction is detected while operating in the software mode.

4. The method of claim 2 , further comprising issuing a commit instruction if a conflicting transaction is not detected.

5. A machine-readable storage medium comprising instructions, which when executed, cause a machine to perform a method, the method comprising:

selecting, from among modes having a hardware mode and a software mode, the hardware mode to implement transactional memory accesses including detecting an orphan transaction, the orphan transaction including an uncommitted transaction capable of corrupting a memory or a corresponding software program, the hardware mode to utilize a transaction cache of a processor, the software mode to utilize a regular cache of the processor; and

invoking, via the hardware mode utilizing the transaction cache, an orphan transaction exception in lieu of a transaction validate instruction to asynchronously notify a thread of the detection of the orphan transaction, the notification to prevent the orphan transaction from corrupting the memory or the corresponding software program.

6. The machine-readable storage medium of claim 5 , having further instructions that when executed cause the machine to perform a further method comprising:

selecting the software mode if an abort instruction is issued in the hardware mode; and

invoking the orphan transaction exception in lieu of the transaction validate instruction via the software mode utilizing the regular cache.

7. The machine-readable storage medium of claim 6 , having further instructions that when executed cause the machine to perform a further method comprising:

issuing an abort instruction if a conflicting transaction is detected in the software mode.

8. The machine-readable storage medium of claim 6 , having further instructions that when executed cause the machine to perform a further method comprising:

issuing a commit instruction if a conflicting transaction is not detected.

9. A computer system comprising:

a processor having a transactional cache and a regular cache, wherein the transactional cache is associated with a hardware mode and the regular cache is associated with a software mode; and

a policy manager to select the hardware mode or the software mode to implement transactional memory accesses including detecting an orphan transaction, the orphan transaction including an uncommitted transaction capable of corrupting a memory or a corresponding software program, the hardware mode to utilize the transaction cache and the software mode to utilize the regular cache, and

wherein the hardware mode utilizing the transaction cache to invoke an orphan transaction exception in lieu of a transaction validate instruction to asynchronously notify a thread of the detection of the orphan transaction, and wherein the notification to prevent the orphan transaction from corrupting the memory or the corresponding software program.

10. The computer system of claim 9 , wherein, if an abort instruction is issued for the hardware mode, the policy manager to select the software mode utilizing the regular cache to invoke the orphan transaction exception in lieu of the transaction validate instruction.

11. The computer system of claim 10 , wherein, operating in the software mode, if a conflicting transaction is detected, an abort instruction is issued.

12. The computer system of claim 10 , wherein, if a conflicting transaction is not detected, a commit instruction is issued.

13. A processor comprising:

a transactional cache and a regular cache, wherein the transactional cache is associated with a hardware mode and the regular cache is associated with a software mode; and

a policy manager to select the hardware mode or the software mode to implement transactional memory accesses and to detect an orphan transaction, the orphan transaction including an uncommitted transaction capable of corrupting a memory or a corresponding software program, the hardware mode to utilize the transaction cache and the software mode to utilize the regular cache,

wherein the hardware mode utilizing the transactional cache to invoke an orphan transaction exception in lieu of a transaction validate instruction to asynchronously notify a thread of the detection of the orphan transaction, and wherein the notification to prevent the orphan transaction from corrupting the memory or the corresponding software program.

14. The processor of claim 13 , wherein, if an abort instruction is issued for the hardware mode, the policy manager to select the software mode utilizing the regular cache to invoke the orphan transaction exception in lieu of the transaction validate instruction.

15. The processor of claim 14 , wherein, operating in the software mode, if a conflicting transaction is detected, an abort instruction is issued.

16. The processor of claim 14 , wherein, if a conflicting transaction is not detected, a commit instruction is issued.

17. A method comprising:

selecting, from among modes having a hardware mode and a software mode, the hardware mode before selecting the software mode to implement transactional memory accesses including detecting initiating of a lock acquire function, wherein the lock acquire function is initiated to acquire a lock in a lock-based programming system, wherein the hardware mode to utilize a transaction cache of a processor, and wherein the software mode to utilize a regular cache of the processor;

entering by a thread a critical section without marking it as locked to abort any other threads already in the hardware mode; and

executing, via the hardware mode utilizing the transaction cache, the critical section that refers to a programming code section being executed between an acquisition of the lock and a subsequent release of the lock.

18. The method of claim 17 , further comprising automatically triggering the software mode utilizing the regular cache resident to execute the critical section if the hardware mode fails and an abort instruction is issued.

19. The method of claim 17 , further comprising:

verifying by the thread if the lock is available;

preventing by the thread any new threads from entering the critical section in the hardware mode.

20. The method of claim 17 , further comprising:

verifying by a thread if the lock is available; and

entering the critical section by marking it as locked to prevent any new threads from entering the critical section in the software mode.

21. A machine-readable storage medium having instructions, which when executed, cause a machine to perform a method, the method comprising:

selecting, from among modes having a hardware mode and a software mode, the hardware mode before selecting the software mode to implement transactional memory accesses including detecting initiating of a lock acquire function, wherein the lock acquire function is initiated to acquire a lock in a lock-based programming system, wherein the hardware mode to utilize a transaction cache of a processor, and wherein the software mode to utilize a regular cache of the processor;

entering by a thread a critical section without marking it as locked to abort any other threads already in the hardware mode; and

executing, via the hardware mode utilizing the transaction cache the critical section that refers to a programming code section being executed between an acquisition of the lock and a subsequent release of the lock.

22. The machine-readable storage medium of claim 21 , having further instructions that when executed cause the machine to perform a further method comprising:

automatically triggering the software mode utilizing the regular cache to execute the critical section if the hardware mode fails and an abort instruction is issued.

23. The machine-readable storage medium of claim 21 , having further instructions that when executed cause the machine to perform a further method comprising:

verifying by the thread if the lock is available when entering the critical section of the lock in the hardware mode; and

preventing by the thread any new threads from entering the critical section in the hardware mode.

24. The machine-readable storage medium of claim 21 , having further instructions that when executed cause the machine to perform a further method comprising:

verifying by a thread if the lock is available when entering the critical section of the lock in the software mode; and

entering the critical section marking it as locked to prevent any new threads from entering the critical section in the software mode.

25. A computer system comprising:

a processor including a transactional cache and a regular cache;

a policy manager to select, from among modes having a hardware mode and a software mode, the hardware mode before selecting the software mode to implement transactional memory accesses and to detect initiating of a lock acquire function, wherein the lock acquire function is initiated to acquire a lock in a lock-based programming system, wherein the hardware mode to utilize the transaction cache and the software mode to utilize the regular cache, and

a thread to enter a critical section without marking it as locked to abort any other threads already in the hardware mode,

wherein the hardware mode utilizing the transaction cache to execute the critical section that refers to a programming code section being executed between an acquisition of the lock and a subsequent release of the lock.

26. The computer system of claim 25 , wherein the policy manager is further to automatically trigger the software mode utilizing the regular cache to execute the critical section if the hardware mode fails and an abort instruction is issued.

27. The computer system of claim 25 , further comprising the thread to:

verify if the lock is available when entering the critical section of the lock in the hardware mode, and

prevent any new threads from entering the critical section in the hardware mode.

28. The computer system of claim 25 , further comprising a thread to:

verify if the lock is available when entering the critical section of the lock in the software mode, and

enter the critical section marking it as locked to prevent any new threads from entering the critical section in the software mode.

29. A processor comprising:

a transactional cache and a regular cache, wherein the transactional cache is associated with a hardware mode and the regular cache is associated with a software mode;

a policy manager to select, from among modes having a hardware mode and a software mode, the hardware mode before selecting the software mode to implement transactional memory accesses and to detect initiating of a lock acquire function, wherein the lock acquire function is initiated to acquire a lock in a lock-based programming system, wherein the hardware mode to utilize the transaction cache and the software mode to utilize the regular cache; and

a thread to enter a critical section without marking it as locked to abort any other threads already in the hardware mode,

wherein the hardware mode utilizing the transaction cache to execute the critical section that refers to a programming code section being executed between an acquisition of the lock and a subsequent release of the lock.

30. The processor of claim 29 , wherein the policy manager is further to automatically trigger the software mode utilizing the regular cache to execute the critical section if the hardware mode fails and an abort instruction is issued.

31. The processor of claim 29 , further comprising the thread to:

verify if the lock is available when entering the critical section of the lock in the hardware mode, and

prevent any new threads from entering the critical section in the hardware mode.

32. The processor of claim 29 , further comprising a thread to:

verify if the lock is available when entering the critical section of the lock in the software mode, and

enter the critical section marking it as locked to prevent any new threads from entering the critical section in the software mode.