Integration for buried epitaxial stressor
View Patent ↗Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the stressor layer. We form STI trenches down through the strained layer and the stressor layer to as least partially expose the buried doped regions. We etch the buried doped regions to form at least a buried cavity in communication with the STI trenches. In the first and second embodiments, we fill only the STI trenches with insulation material to form isolation regions and form voids in the cavities. In the third and fourth embodiments, we fill both the STI trenches and the cavities with insulation material.
1. A method of fabricating a semiconductor device comprising:
providing a substrate comprising a first device region;
forming at least one doped region in the substrate;
forming a stressor layer over the substrate, the stressor layer comprising a semiconductor stressor material;
forming a semiconductor surface layer over the stressor layer; and
selectively removing the at least one doped region to form at least one buried cavity in the first device region, the buried cavity is disposed below the stressor layer, the buried cavity causing the stressor layer to have a relaxed portion overlying the buried cavity;
forming a first transistor in the first device region; and
wherein the stressor layer is a continuous stressor layer in the first device region, the relaxed portion of the continuous stressor layer caused by the buried cavity below creates a first strain in the surface layer to enhance performance of the first transistor in the first device region.
2. The method of claim 1 wherein:
forming at least one doped region comprises forming first and second doped regions;
removing the first and second doped regions forms first and second buried cavities; and
wherein the first transistor comprising a gate, and source and drain regions adjacent to the gate,
wherein the first and second buried cavities are at least partially under the source and drain regions.
3. The method of claim 1 wherein the substrate is comprised of silicon and the doped region is formed by implanting a N-type dopant and annealing the substrate.
4. The method of claim 1 wherein said stressor layer is comprised of SiGe or SiGeC.
5. The method of claim 1 wherein the surface layer is comprised of Si or carbon doped silicon.
6. A method for forming a device comprising:
providing a substrate comprising a first device region;
forming a stressor layer over the substrate, the stressor layer comprising a semiconductor stressor material;
forming a semiconductor surface layer over the stressor layer; and
forming at least one buried cavity in the first device region under the stressor layer, the buried cavity causing the stressor layer to comprise at least one relaxed portion overlying the buried cavity;
forming a first transistor in the first device region; and
wherein the stressor layer is a continuous stressor layer in the first device region the relaxed portion of the continuous stressor layer creates a first strain in the surface layer to enhance performance of the first transistor in the first device region.
7. The method of claim 6 wherein forming at least one buried cavity comprises forming first and second buried cavities below source and drain regions of the first transistor in the first device region.
8. The method of claim 6 wherein the at least one buried cavity is formed below a channel region of the first transistor in the first device region.
9. The method of claim 6 wherein forming the buried cavity comprises:
forming a doped region within the substrate in a defined portion of the first device region; and
forming a shallow trench isolation to isolate the first device region.
10. The method of claim 9 wherein forming the shallow trench isolation comprises:
etching the substrate to form a trench for the shallow trench isolation, wherein etching removes portion of the substrate corresponding to the doped region; and
filling the trench to form the shallow trench isolation and the buried cavity in the removed doped portion of the substrate.
11. The method of claim 6 wherein the strained portion of the stressor layer has about a same lattice constant as the surface layer.
12. The method of claim 11 wherein the relaxed portion of the stressor layer has a larger lattice constant than the surface layer.
13. The method of claim 12 wherein the relaxed portion of the stressor layer is formed below a channel region of the first transistor in the first device region and the first strain is a tensile stress generated in the channel region.
14. The method of claim 12 wherein the relaxed portion of the stressor layer is formed below a source and drain region of the first transistor in the first device region and the first strain is a compressive stress generated in a channel region of the first transistor.
15. The method of claim 6 wherein the relaxed portion of the stressor layer is formed below a channel region of the first transistor in the first device region and the first strain is a tensile stress generated in the channel region.
16. The method of claim 6 wherein the relaxed portion of the stressor layer is formed below a source and drain region of the first transistor in the first device region and the first strain is a compressive stress generated in a channel region of the first transistor.
17. The method of claim 6 wherein forming the buried cavity comprises:
forming a doped region within the substrate in a defined portion of the first device region and selectively removing the doped region.
18. The method of claim 17 comprising forming the doped region before forming the stressor layer and semiconductor surface layer.
19. The method of claim 17 comprising selectively removing the doped region after forming the stressor layer and semiconductor surface layer.
20. The method of claim 6 wherein the at least one buried cavity is filled with insulation material.
21. The method of claim 6 further comprising forming a first gate stack over the surface layer after forming the at least one buried cavity wherein the first gate stack is associated with the first transistor.