IP Library Granted Patent US 7,877,521
Granted Patent B2
US 7,877,521 · App. 11/836,357 · Granted Jan 25, 2011

Processing apparatus and method of modifying system configuration

Assignee: NEC Corporation
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Quick Facts
Patent No.
US 7,877,521
App. No.
11/836,357
Granted
Jan 25, 2011
Kind
B2
Abstract

A virtual PCI Express device 1600 indicates the presence of a pseudo I/O device in a PCI Express initial configuration cycle to reserve a resource space for a device anticipated to be installed in the future, and when an I/O device 1400 is inserted into an unoccupied slot 1605 , a virtual PCI Express device control logic 1602 notifies a downstream PCI-PCI bridge 1504 via a hot-plugging control line 1601 , and the downstream PCI-PCI bridge 1504 generates an interrupt to a CPU 1100 to notify it of insertion of the I/O device 1400 in conformance with the procedure for hot plugging defined by the PCI-SIG Standards, and configuration software 1000 invoked configures the inserted I/O device 1400.

Claims (38)

1. A processing apparatus connected to a bus, comprising:

a slot;

a pseudo-device comprising one or more configuration registers, and a control section which performs write and read operations on the configuration registers, and transmitting information containing a request for a resource space of a device to a CPU, wherein the pseudo-device mimics a response indicating that the device is present; and

a communication relay which relays communication between said bus and said pseudo-device when the device for using the resource space reserved by said pseudo-device is not connected to said slot, and for relaying communication between said bus and said slot when said device is connected to said slot.

2. A processing apparatus according to claim 1 , wherein said pseudo-device retains topology information of said pseudo-device itself, and said controller performs write and read operations on said configuration registers based on said topology information.

3. A processing apparatus according to claim 1 , wherein when the device has been inserted into said slot, said control section generates an interrupt to the CPU by notifying a neighboring downstream bridge of insertion of the device.

4. A processing apparatus according to claim 1 , wherein said controller generates a first interrupt to a CPU when a device is removed from said slot and said slot is an unoccupied slot, and generates a second interrupt to said CPU when a new device is inserted into said unoccupied slot.

5. A processing apparatus according to claim 1 , wherein said controller uses information on a resource space allocated to said pseudo-device to partially or fully make a configuration on said device inserted into said slot.

6. A processing apparatus according to claim 5 , wherein said controller generates an interrupt to a CPU upon completion of said configuration.

7. A processing apparatus according to claim 6 , wherein said configuration made by said controller before generating said interrupt is directed to a device which is not supported by configuration on a device made by configuration software activated by an interrupt to said CPU.

8. A processing apparatus according to claim 3 , wherein said interrupt is in compliance with a procedure for hot plugging defined by PCI-SIG Standards.

9. A processing apparatus according to claim 1 , wherein standards of said bus are PCI.

10. A processing apparatus according to claim 1 , wherein standards of said bus are PCI-X.

11. A processing apparatus according to claim 1 , wherein standards of said bus are PCI Express.

12. A processing apparatus according to claim 11 , wherein said processing apparatus is connected to or incorporated into a device constituting a PCI Express switch.

13. A processing apparatus according to claim 12 , wherein said device to be connected to said slot is any one of an I/O device, a PCI Express switch, and a downstream PCI-PCI bridge.

14. A processing apparatus according to claim 11 , wherein said processing apparatus is connected to or incorporated into a device constituting a root complex.

15. A processing apparatus according to claim 14 , wherein said device to be connected to said slot is any one of an I/O device and a PCI Express switch.

16. The processing apparatus according to claim 1 , wherein during an initial configuration by configuration software executed by a CPU in a system upstream of said bus from said processing apparatus and wherein no device is connected to said slot, said configuration software allocates resource space to said pseudo-device; and

when a device is inserted into said slot, at least a portion of said resource space allocated to said pseudo-device is allocated to said device inserted into said slot.

17. A method of modifying a system configuration, comprising:

making an initial configuration by configuration software executed by a CPU in a system with a processing apparatus incorporated into said system, said processing apparatus connected to a bus, and comprising a slot, a pseudo-device comprising one or more configuration registers and a control section which performs write and read operations on the configuration registers, and transmitting information containing a request for a resource space of a device to a CPU, wherein the pseudo-device mimics a response indicating that the device is present, and a communication relay which relays communication between said bus and said pseudo-device when the device for using the resource space reserved by said pseudo-device is not connected to said slot, and for relaying communication between said bus and said slot when the device is connected to said slot; and

when a device is inserted into said slot, making a configuration on said inserted device.

18. A method of modifying a system configuration according to claim 17 , wherein said pseudo-device retains topology information of said pseudo-device itself, and said controller performs write and read operations on said configuration registers based on said topology information.

19. A method of modifying a system configuration according to claim 17 , wherein when the device has been inserted into said slot, said control section generates an interrupt to the CPU by notifying a neighboring downstream bridge of insertion of the device.

20. A method of modifying a system configuration according to claim 17 , wherein said controller generates a first interrupt to a CPU when a device is removed from said slot and said slot is an unoccupied slot, and generates a second interrupt to said CPU when a new device is inserted into said unoccupied slot.

21. A method of modifying a system configuration according to claim 17 , wherein, said controller uses information on a resource space allocated to said pseudo-device during said initial configuration, to partially or fully make a configuration on said device inserted into said slot.

22. A method of modifying a system configuration according to claim 21 , wherein said controller generates an interrupt to said CPU upon completion of said configuration.

23. A method of modifying a system configuration according to claim 22 , wherein said configuration made by said controller before generating said interrupt is directed to a device which is not supported by configuration on a device made by configuration software activated by an interrupt to said CPU.

24. A method of modifying a system configuration according to claim 19 , wherein said interrupt is in compliance with a procedure for hot plugging defined by PCI-SIG Standards.

25. A method of modifying a system configuration according to claim 24 , wherein said configuration made by said configuration software activated by said interrupt is in compliance with said procedure for hot plugging defined by said PCI-SIG Standards.

26. A method of modifying a system configuration according to claim 17 , wherein standards of said bus are PCI.

27. A method of modifying a system configuration according to claim 17 , wherein standards of said bus are PCI-X.

28. A method of modifying a system configuration according to claim 17 , wherein standards of said bus are PCI Express.

29. A method of modifying a system configuration according to claim 28 , wherein said processing apparatus is connected to or incorporated into a device constituting a PCI Express switch, and said device to be connected to said slot is any one of an I/O device, a PCI Express switch, and a downstream PCI-PCI bridge.

30. A method of modifying a system configuration according to claim 28 , wherein said processing apparatus is connected to or incorporated into a device constituting a root complex, and said device to be connected to said slot is any one of an I/O device and a PCI Express switch.

31. The method of modifying a system configuration according to claim 17 , wherein during said making of said initial configuration by configuration software and wherein no device is connected to said slot, said configuration software allocates resource space to said pseudo-device; and

when a device is inserted into said slot, at least a portion of said resource space allocated to said pseudo-device is allocated to said device inserted into said slot.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2007
From: SUZUKI, JUN; HIDAKA, YOUICHI; HIGUCHI, JUNICHI; IWATA, ATSUSHI
To: NEC CORPORATION
Reel/Frame 019673/0335 →
Priority Claims (1)
JP 2006-219469 · Aug 11, 2006 · national
Continuity (1)
Related Publication 20080040526A1 · Feb 14, 2008