Digital camera with multiple pipeline signal processors
View Patent ↗There are many, many inventions described herein. In one aspect, what is disclosed is a digital camera including a plurality of arrays of photo detectors, including a first array of photo detectors to sample an intensity of light of a first wavelength and a second array of photo detectors to sample an intensity of light of a second wavelength. The digital camera further may also include a first lens disposed in an optical path of the first array of photo detectors, wherein the first lens includes a predetermined optical response to the light of the first wavelength, and a second lens disposed in with an optical path of the second array of photo detectors wherein the second lens includes a predetermined optical response to the light of the second wavelength. In addition, the digital camera may include signal processing circuitry, coupled to the first and second arrays of photo detectors, to generate a composite image using (i) data which is representative of the intensity of light sampled by the first array of photo detectors, and (ii) data which is representative of the intensity of light sampled by the second array of photo detectors; wherein the first array of photo detectors, the second array of photo detectors, and the signal processing circuitry are integrated on or in the same semiconductor substrate.
1. A digital camera comprising:
a plurality of arrays of photo detectors, including:
a first array of photo detectors to sample an intensity of light; and
a second array of photo detectors to sample an intensity of light;
a first channel processor coupled to the first array and configured to generate a first image using first array data which is representative of the intensity of light sampled by the first array;
a second channel processor coupled to the second array and configured to generate a second image using second array data which is representative of the intensity of light sampled by the second array; and
a semiconductor substrate, wherein the first array, the second array, the first channel processor and the second channel processor are integrated on or in the substrate.
2. The camera of claim 1 , wherein the first channel processor is configured to generate first control data to control a first camera channel that includes the first array and the first channel processor.
3. The camera of claim 2 , wherein the second channel processor is configured to generate second control data to control a second camera channel that includes the second array and the second channel processor.
4. The camera of claim 3 , wherein the first channel processor controls the first camera channel to operate as a stand-alone imager.
5. The camera of claim 3 , wherein the first channel processor controls the first camera channel to operate in combination with the second camera channel.
6. The camera of claim 3 , wherein the second channel processor controls the second camera channel to operate as a stand-alone imager.
7. The camera of claim 3 , wherein the second channel processor controls the second camera channel to operate in combination with the first camera channel.
8. The camera of claim 3 , wherein the first channel processor is configured to process the first array data of light of a first wavelength.
9. The camera of claim 8 , wherein the second channel processor is configured to process the second array data of light of a second wavelength.
10. The camera of claim 3 , wherein the first channel processor is configured to process the first array data of light of a first set of wavelengths.
11. The camera of claim 10 , wherein the second channel processor is configured to process the second array data of light of a second set of wavelengths.
12. The camera of claim 11 , wherein the first set of wavelengths and the second set of wavelengths each include at least one common wavelength.
13. The camera of claim 3 , wherein the first channel processor is configured to control a gain of the first camera channel and the second channel processor is configured to control a gain of the second camera channel.
14. The camera of claim 3 , wherein the first channel processor is configured to control noise of the first camera channel and the second channel processor is configured to control noise of the second camera channel.
15. The camera of claim 3 , wherein the first channel processor is configured to control dynamic range of the first camera channel and the second channel processor is configured to control dynamic range of the second camera channel.
16. The camera of claim 3 , wherein the first channel processor is configured to control linearity of the first camera channel and the second channel processor is configured to control linearity of the second camera channel.
17. The camera of claim 3 , wherein the first channel processor is configured to control exposure of the first camera channel and the second channel processor is configured to control exposure of the second camera channel.
18. The camera of claim 3 , wherein the first channel processor is configured to control double sampling of the first camera channel and the second channel processor is configured to control double sampling of the second camera channel.
19. The camera of claim 3 , wherein the first channel processor is configured to control black level clamp of the first camera channel and the second channel processor is configured to control black level clamp of the second camera channel.
20. The camera of claim 3 , wherein the first channel processor is configured to control pixel substitution of the first camera channel and the second channel processor is configured to control pixel substitution sampling of the second camera channel.
21. The camera of claim 3 , wherein the first channel processor is configured to control an integration time of the first camera channel and the second channel processor is configured to control an integration time of the second camera channel.
22. The camera of claim 21 , wherein the first channel processor is configured to control the integration time using a first integration time and the second channel processor is configured to control the integration time using a second integration time, wherein the first integration time is different than the second integration time.
23. The camera of claim 1 , comprising a pipeline processor coupled to the first channel processor and the second channel processor, the pipeline processor configured to generate a composite image using data of the first image and the second image.
24. The camera of claim 23 , wherein the pipeline processor is configured to generate control data to control a first camera channel that includes the first array and the first channel processor and a second camera channel that includes the second array and the second channel processor.
25. The camera of claim 24 , wherein the pipeline processor is configured to control, the intensity of light from the first camera channel and the second camera channel.
26. The camera of claim 23 , wherein the pipeline processor is integrated on or in the substrate.
27. The camera of claim 23 , wherein the pipeline processor is configured to perform analog and digital signal processing.
28. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including color space conversion.
29. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including channel mapping.
30. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including exposure control.
31. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including integration time control of at least one of the plurality of arrays of photo detectors.
32. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including pixel correction.
33. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including double sampling.
34. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including image/color plane integration.
35. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including parallax estimation and correction.
36. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including image plane alignment and stitching.
37. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including pixel binning and windowing.
38. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including image interpolation.
39. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including focus control.
40. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including gamma control.
41. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including color correction.
42. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including enhancement and balance.
43. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including edge enhancement and image sharpening.
44. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including chroma and random noise reduction.
45. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including white balance.
46. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including image scaling.
47. The camera of claim 23 , wherein the pipeline processor is configured to perform processing including zoom and resizing.
48. The camera of claim 1 , comprising a postprocessor coupled to the pipeline processor.
49. The camera of claim 48 , wherein the postprocessor is integrated on or in the substrate.
50. The camera of claim 48 , wherein the postprocessor is configured to perform analog and digital signal processing.
51. The camera of claim 48 , wherein the postprocessor is configured to perform processing selected from a group consisting of downsampling, still image encoding, video encoding, frame buffering, and output interfacing.
52. The camera of claim 1 , comprising timing and control logic configured to provide timing and control information to the first channel processor and the second channel processor.
53. The camera of claim 52 , wherein the timing and control logic is integrated on or in the substrate.
54. The camera of claim 1 , comprising a memory configured to store the first array data and the second array data.
55. The camera of claim 54 , wherein the memory is integrated on or in the substrate.
56. The camera of claim 1 , comprising a frame including a spacer and a support, wherein the spacer is mounted on the substrate and includes a lower set of apertures, wherein the support is detachably coupled to the spacer and includes an upper set of apertures, wherein the lower and upper set of apertures form a discontinuous optical path to the photo detectors.
57. The camera of claim 56 , comprising a plurality of optics components, wherein each optics component includes a plurality of optical lenses and a lens barrel configured to position and hold the plurality of optical lenses.
58. The camera of claim 57 , wherein a first configuration of a first optics component is different from a second configuration of a second optics component.