System and method for implementing irregular data formats

1. A computer system comprising:

a processing unit configured to process fixed size data words comprising two separate exponent fields, at least one of the exponent fields of variable size, and a mantissa of variable size;

an input device configured to provide data words to the processing unit; and

an output device configured to output data words processed by the processing unit.

2. The computer system of claim 1 , wherein the processing unit is configured to process one of 8-bit fixed size data words, 16-bit fixed size data words, 24-bit fixed size data words and 32-bit fixed size data words.

3. The computer system of claim 1 wherein the processing unit comprises:

a first entrance format converter;

a second entrance format converter;

wherein each of the first and second entrance format converters is configured to receive and convert a data word comprising at least one exponent field of variable size and a mantissa of variable size into a fixed point data word format; and

a multiply accumulate circuit (MAC) configured to multiply the converted data word from the first entrance format converter with the converted data word from the second entrance format converter and accumulate the result of the multiplication.

4. The computer system of claim 3 , wherein the processing unit further comprises an exit format converter configured to convert the accumulated result of the multiplication into a data word format comprising at least one exponent field and a mantissa, each of varying size.

5. The computer system of claim 1 , wherein the processing unit is configured to map an exponent component from each of the two separate exponent fields to a single binary exponent.

6. The computer system of claim 1 , wherein the input device comprises one of a sensor, a receive antenna, a keyboard, a number pad, a mouse, and a touchscreen.

7. The computer system of claim 1 , wherein the output device comprises one of a speaker, a display element, and a transmit antenna.

8. A digital signal processing unit comprising:

a first entrance format converter;

a second entrance format converter;

wherein each of the first and second entrance format converters is configured to receive and convert a data word comprising at least one exponent field of variable size and a mantissa of variable size into a fixed point data word format; and

a multiply accumulate circuit (MAC) configured to multiply the converted data word from the first entrance format converter with the converted data word from the second entrance format converter and accumulate the result of the multiplication.

9. The digital signal processing unit of claim 8 , further comprising an exit format converter configured to convert the accumulated result of the multiplication into a data word format comprising at least one exponent field and a mantissa, each of varying size.

10. The digital signal processing unit of claim 8 , wherein the first and second entrance format converters are configured to pass received fixed point data words to the multiply accumulate circuit without conversion.

11. The digital signal processing unit of claim 8 , wherein the multiply accumulate circuit comprises:

a 16-bit by 16-bit multiplier configured to multiply together the converted data word from each of the entrance format converters; and

a 48-bit accumulator configured to accumulate the result of the multiplication.

12. A program product comprising program instructions embodied on a processor-readable medium for execution by a programmable processor, wherein the program instructions are operable to cause the programmable processor to:

detect a first exponent field in a received data word of fixed size;

detect a second exponent field in the data word;

derive two exponent components, one exponent component from the first detected exponent field and one exponent component from the second detected exponent field; and

map the two exponent components into a single binary exponent.

13. The program product of claim 12 , wherein the program instructions are further operable to cause the programmable processor to:

detect the first exponent field by locating a first pattern of logical zeros separated from the mantissa of the data word by a logical one; and

detect the second exponent field by locating a second pattern of logical zeros separated from the mantissa of the data word by a logical one.

14. The program product of claim 13 , wherein the program instructions are further operable to cause the programmable processor to:

derive two exponent components from the first and second exponent fields by counting the number of logical zeros in each of the first and second exponent fields.

15. The program product of claim 12 , wherein the program instructions are further operable to cause the programmable processor to:

detect the first exponent field by locating a binary number in the most significant bits of the data word; and

detect the second exponent field by locating a pattern of logical zeros separated from the mantissa of the data word by a logical one.

16. The program product of claim 12 , wherein the program instructions are further operable to cause the programmable processor to:

map the two exponent components into a single binary exponent by using one of a lookup table and an algorithm which associates the two exponent components with a single binary exponent.

17. The program product of claim 12 , wherein the program instructions are further operable to cause the programmable processor to:

format a new data word of fixed size with a mantissa and at least one exponent field, wherein the size of the mantissa and the size of the at least one exponent field vary based, at least in part, on a numerical value being represented by the new data word.

18. The program product of claim 17 , wherein the program instructions are further operable to cause the programmable processor to:

output the new data word to an output device.

19. The program product of claim 12 , wherein the program instructions are further operable to cause the programmable processor to:

convert the received data word to a fixed point data word format.