Semiconductor devices having selectively tensile stressed gate electrodes and methods of fabricating the same
A semiconductor device includes an active region. A gate electrode is disposed on the active region. An isolation region adjoins the active region, and is recessed with respect to a top surface of the active region underlying the gate electrode. The isolation region may be recessed a depth substantially equal to a height of the gate electrode. In some embodiments, the gate electrode is configured to support current flow through the active region along a first direction, and a tensile stress layer covers the gate electrode and is configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction. The tensile stress layer may cover the recessed isolation region and portions of the active region between the isolation region and the gate electrode. In further embodiments, an interlayer insulating film is disposed on the tensile stress layer and is configured to apply a tensile stress to the gate electrode along the second direction.
1. A semiconductor device comprising:
an active region;
a gate electrode on the active region; and
an isolation region adjoining a sidewall of the active region, the isolation region recessed with respect to a top surface of the active region underlying the gate electrode, wherein a top surface of a portion of the isolation region positioned below and overlapped by the gate electrode is lower than the top surface of the active region underlying the gate electrode.
2. The semiconductor device of claim 1 , wherein the gate electrode is configured to support current flow through the active region along a first direction, and further comprising a tensile stress layer covering the gate electrode and configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction.
3. The semiconductor device of claim 2 , wherein the tensile stress layer covers the recessed isolation region and portions of the active region between the isolation region and the gate electrode.
4. The semiconductor device of claim 2 , further comprising an interlayer insulating film on the tensile stress layer, the interlayer insulating film configured to apply a tensile stress to the gate electrode along the second direction.
5. The semiconductor device of claim 1 , further comprising:
an etching stop film surrounding the gate electrode; and
an interlayer insulating film formed on the etching stop film, the interlayer insulating film having a tensile stress.
6. The semiconductor device of claim 1 , wherein the isolation region is recessed a depth substantially equal to a height of the gate electrode.
7. The semiconductor device of claim 1 , further comprising a sidewall spacer disposed on a sidewall of the gate electrode, wherein a top surface of the active region between the spacer and the isolation region is lower than the top surface of the active region underlying the gate electrode.
8. The semiconductor device of claim 7 , wherein the top surface of the isolation region is lower than the top surface of the active region between the spacer and the isolation region.
9. A method of fabricating a semiconductor device, the method comprising:
forming a isolation region in a semiconductor substrate to define an active region in the semiconductor substrate, the isolation region adjoining a sidewall of the active region; and
forming a gate electrode on the active region,
wherein the isolation region is recessed with respect to a top surface of the active region underlying the gate electrode, and
wherein a top surface of a portion of the isolation region positioned below and overlapped by the gate electrode is lower than the top surface of the active region underlying the gate electrode.
10. The method of claim 9 , wherein the gate electrode is configured to support current flow through the active region along a first direction, and wherein the method further comprises forming a tensile stress layer covering the gate electrode and configured to apply a tensile stress to the gate electrode along a second direction perpendicular to the first direction.
11. The method of claim 10 , wherein the tensile stress layer covers the recessed isolation region and portions of the active region between the isolation region and the gate electrode.
12. The method of claim 10 , further comprising forming an interlayer insulating film on the tensile stress layer, the interlayer insulating film configured to apply a tensile stress to the gate electrode along the second direction.
13. The method of claim 10 , wherein the tensile stress layer is formed by an LPCVD or PECVD process.
14. The method of claim 10 , further comprising:
forming an etching stop film surrounding the gate electrode; and
forming an interlayer insulating film on the etching stop film, the interlayer insulating film having a tensile stress.
15. The method of claim 9 , wherein the isolation region is recessed to a depth substantially equal to a height of the gate electrode.
16. The method of claim 9 , wherein forming an isolation region in the semiconductor substrate to define an active region in the semiconductor substrate comprises etching to recess the isolation region with respect to the top surface of the active region.
17. The method of claim 16 , further comprising forming a silicide layer on the active region between the isolation region and the gate electrode after etching the isolation region.
18. The method of claim 16 , further comprising forming a spacer on a sidewall of the gate electrode and etching a portion of the active region between the spacer and the isolation region using the spacer as an etching mask before etching to recess the isolation region, such that a top surface of the active region between the gate electrode and the isolation region is lower than the top surface of the active region underlying the gate electrode.
19. The method of claim 18 , further comprising forming a silicide layer on the recessed portion of the active region between the gate electrode and the isolation region.
20. The method of claim 18 , wherein the top surface of the isolation region is lower than the top surface of the active region between the gate electrode and the isolation region.