Low voltage low cost non-volatile memory

1. A non-volatile memory (NVM) cell, comprising:

a) a floating gate in a gate layer, said floating gate being partially over a first insulating layer, said first insulating layer being over a first channel between first and second diffusion regions; and

b) a control gate in said gate layer, wherein said control gate is configured to control said floating gate using direct sidewall capacitive coupling, and wherein a first coupling ratio from said direct sidewall capacitive coupling is greater than a second coupling ratio from said second diffusion region.

2. The NVM cell of claim 1 , wherein said insulating layer comprises oxide.

3. The NVM cell of claim 1 , wherein said gate layer comprises polysilicon.

4. The NVM cell of claim 1 , wherein said gate layer comprises metal.

5. The NVM cell of claim 1 , wherein said first coupling ratio is greater than about 0.3.

6. The NVM cell of claim 1 , wherein said second coupling ratio is less than about 0.2.

7. The NVM cell of claim 1 , wherein a minimum spacing between said floating gate and said control gate is about twice a minimum feature size.

8. The NVM cell of claim 1 , wherein said control gate is over second and third insulating layers, said second insulating layer being over a second channel between said second and a third diffusion regions.

9. The NVM cell of claim 8 , wherein said first insulating layer is a tunnel oxide.

10. The NVM cell of claim 8 , wherein said third insulating layer is a field oxide.

11. The NVM cell of claim 8 , wherein said first diffusion region is a drain and said third diffusion region is a source.

12. The NVM cell of claim 1 , wherein:

a) a first portion of said floating gate is arranged substantially over an active transistor region;

b) a second portion of said floating gate is arranged substantially over a field region; and

c) said control gate is over said field region and substantially parallel to said second portion of said floating gate.

13. The NVM cell of claim 1 , wherein said control gate is configured to span across a plurality of active regions and field regions, and wherein said floating gate is substantially parallel to said control gate.

14. The NVM cell of claim 1 , configured to be programmed using channel hot electrons (CHE) through said first insulating layer.

15. The NVM cell of claim 1 , configured to be erased using channel-induced hot holes (CHH) through said first insulating layer.

16. The NVM cell of claim 15 , further configured to be erased by ramping down a voltage on said control gate.

17. An electrically erasable programmable read-only memory (EEPROM) device, comprising:

a) a controller configured to control programming, erasing, and reading of a memory portion; and

b) said memory portion having a plurality of non-volatile memory (NVM) cells, wherein each said NVM cell comprises: (i) a floating gate in a gate layer, said floating gate being over an insulating layer, said insulating layer being over a first channel between first and second diffusion regions; and (ii) a control gate in said gate layer, wherein said control gate is configured to control said floating gate using direct sidewall capacitive coupling, and wherein a first coupling ratio from said direct sidewall capacitive coupling is greater than a second coupling ratio from said second diffusion region.

18. The EEPROM device of claim 17 , wherein said erasing comprises using channel-induced hot holes (CHH) through said insulating layer.