Cellular engine for a data processing system

1. A cellular engine for a data processing system, said engine comprising:

an associative memory device having n-cells, each of said n-cells being able to store m bits;

a vector memory containing p-vectors, each of said p-vectors having a storage capacity of n×m-bits;

a control interconnection network that for each of said n-cells generates a classification code that classifies a cell in dependence upon a local state and a global state of said cell;

an instruction register for accepting an instruction issued from a controller;

a clock device for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second, said clock device outputting said synchronizing clock signal to said associative memory device and said vector memory;

and wherein said engine globally communicates said instruction to all of said n-cells simultaneously within one of said clock cycles, said instruction being executed in parallel by selected cells within said associative memory device, all within one of said clock cycles, in accordance with said classification of each of said n-cells by said control interconnection network.

2. The cellular engine for a data processing system according to claim 1 , wherein:

said instruction is executed in parallel by all of said n-cells within said associative memory device.

3. The cellular engine for a data processing system according to claim 1 , further comprising:

a data interconnection network that connects each cell to its right and left neighbors respectively.

4. The cellular engine for a data processing system according to claim 3 , wherein:

both of said data interconnection network and said control interconnection network are expandable.

5. The cellular engine for a data processing system according to claim 1 , wherein:

each of said n-cells includes a state field and a data field, said state field comprising a marker bit for encoding a local state of each of said n-cells; and

wherein said maker bit is in one of a marked state and a non-marked state.

6. The cellular engine for a data processing system according to claim 5 , wherein:

said state field is modified using associative mechanisms as implemented by said execution of said instruction belonging to a specific subset of instructions.

7. The cellular engine for a data processing system according to claim 6 , wherein:

said data field is modified by executing logic and arithmetic instructions in said n-cells in accordance with said classification of each of said n-cells by said control interconnection network.

8. The cellular engine for a data processing system according to claim 1 , wherein:

each of said n-cells in said associative memory device actively processes data.

9. The cellular engine for a data processing system according to claim 1 , wherein:

each of said n-cells in said associative memory device includes a processing circuit.

10. The cellular engine for a data processing system according to claim 1 , wherein said control interconnection network comprises a transcoder that classifies each of said n-cells using corresponding local and global states and a current instruction.

11. The cellular engine for a data processing system according to claim 10 , wherein said transcoder classifies said n-cells into categories comprising a marked cell, a first marked cell, a last marked cell, a cell within stored limits, and an active cell.

12. An engine for a data processing system, said engine comprising:

a memory device containing n-cells;

a controller for selectively issuing an instruction to said memory device;

a cell classification device which operates in association with a local state and a global state of each of said n-cells and generates for each of said n-cells a classification code based on local and global states of said cell;

a clock device for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second, said clock device outputting said synchronizing clock signal to said memory device and said controller; and

wherein said engine globally communicates said instruction to all n-cells simultaneously, within one of said clock cycles; and

wherein said instruction is executed by selected cells within said memory device in dependence upon at least said local state of said n-cells as directed by said cell classification device, said execution of said instruction occurring simultaneously in each of said selected cells within one of said clock cycles.

13. The engine for a data processing system according to claim 12 , wherein:

said instruction is executed by all of said n-cells within said memory device.

14. The engine for a data processing system according to claim 12 , wherein:

said memory device is not conventionally addressed.

15. The engine for a data processing system according to claim 12 , wherein:

said memory device is an associative memory device.

16. The engine for a data processing system according to claim 12 , wherein:

each of said n-cells includes a processing circuit.

17. The engine for a data processing system according to claim 16 , wherein:

said processing circuit has an accumulator.

18. The engine for a data processing system according to claim 12 , wherein:

each of said n-cells includes a field having a marker bit; and

said local state reflects one of a marked state and a non-marked state of said marker bit.

19. The engine for a data processing system according to claim 18 , wherein:

said instruction is executed only within those n-cells having said marker bit set to said marked state.

20. The engine for a data processing system according to claim 12 , wherein:

said instruction is executed by selected cells within said memory device in dependence upon said local state and said global state of said n-cells as directed by said cell classification device, said execution of said instruction occurring simultaneously in each of said selected cells within one of said clock cycles.

21. The engine for a data processing system according to claim 20 , wherein:

said global state utilized by said classification device is determined by said local states of all said n-cells.

22. The engine for a data processing system according to claim 20 , wherein said cell classification device operates in association with corresponding local and global states of each of said n-cells and a current instruction to classify said n-cells into categories comprising a marked cell, a first marked cell, a last marked cell, a cell within stored limits, and an active cell.

23. The engine for a data processing system according to claim 12 , wherein:

each of said n-cells includes a field having a plurality of marker bits.

24. The engine for a data processing system according to claim 12 , wherein said cell classification device operates to transmit to each of said n-cells a corresponding classification code.