IP Library Granted Patent US 7,908,634
Granted Patent B2
US 7,908,634 · App. 12/461,046 · Granted Mar 15, 2011

High-speed cable with embedded power control

Assignee: Redmere Technology Ltd.
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Quick Facts
Patent No.
US 7,908,634
App. No.
12/461,046
Granted
Mar 15, 2011
Kind
B2
Abstract

A High-Definition Multimedia Interface (HDMI) cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Claims (31)

1. A cable for connecting a transmitting data source device to a receiving data sink device, and carrying differential data signals, the cable comprising:

a boost device for boosting at least one of the differential data signals, comprising:

a differential input circuit for receiving one of the differential data signals from the data source device;

a processing block having a transfer function for processing the differential data signal received by the differential input circuit and producing a processed signal;

a differential output circuit for receiving the processed signal, boosting and transmitting a boosted one of the differential data signals to the data sink device, the differential output circuit comprising means for providing electrical power to the processing block; and

an electronic circuit for obtaining at least some electrical power required to operate the processing block from at least one of the differential data signals.

2. The cable as described in claim 1 , wherein the differential data signals are differential High Definition Multi-Media Interface (HDMI) signals, including a plurality of Transition Minimized Differential Signaling (TMDS) encoded data channels and a clock channel.

3. The cable as described in claim 1 , wherein the differential output circuit and the processing block are connected in series so as to conduct a current from the data sink device to a common ground.

4. The cable as described in claim 1 , wherein the boost device further includes a voltage dropper circuit for reducing an available higher voltage and providing a reduced supply voltage for the differential input circuit.

5. The cable as described in claim 4 , wherein the voltage dropper circuit comprises one or more diodes connected in series between the available higher voltage and the reduced supply voltage.

6. The cable as described in claim 4 , wherein the voltage dropper circuit includes switched capacitors, the capacitors used for periodically transferring energy from the available higher voltage node to the reduced supply voltage.

7. The cable as described in claim 1 , wherein the boost device further includes

a voltage generator circuit for obtaining a current from the boosted differential data signal to provide electrical power to the processing block.

8. The cable as described in claim 1 , wherein the electronic circuit includes a voltage generator circuit for obtaining at least one current from the boosted differential signal to provide electrical power to the differential input circuit.

9. The cable as described in claim 8 , wherein the voltage generator circuit includes means for combining the at least one current and adjusting an output voltage of the provided electrical power.

10. The cable as described in claim 1 , wherein the electronic circuit comprises a voltage generator circuit for providing the electrical power to the differential input circuit and the processing block.

11. The cable as described in claim 1 , wherein the processing block includes an equalization circuit for equalizing a frequency response of the cable.

12. The cable as described in claim 1 , wherein the differential output circuit includes means for providing electrical power to the processing block.

13. A boost device for boosting differential data signals sent trough a cable from a transmitting data source device to a receiving data sink device, the boost device comprising:

a differential input circuit for receiving one of the differential data signals from the data source device;

a processing block having a transfer function for processing the differential signal received by the differential input circuit and producing a processed signal;

a differential output circuit for receiving the processed signal, boosting and transmitting a boosted one of the differential data signals to the data sink device, the differential output circuit comprising providing electrical power to the processing block; and

an electronic circuit for obtaining at least some electrical power required to operate the processing block from at least one of the differential data signals.

14. The boost device as described in claim 13 , wherein the differential output circuit and the processing block are connected in series so as to conduct a current from the data sink device to a common ground.

15. The boost device as described in claim 13 , further comprising a voltage dropper circuit for reducing an available higher voltage and providing a reduced supply voltage for the differential input circuit.

16. The boost device as described in claim 15 , wherein the voltage dropper circuit comprises one or more diodes connected in series between the available higher voltage and the reduced supply voltage.

17. The boost device as described in claim 15 , wherein the voltage dropper circuit includes switched capacitors, the capacitors used for periodically transferring energy from the available higher voltage node to the reduced supply voltage.

18. The boost device as described in claim 13 , wherein the boost device further includes

a voltage generator circuit for obtaining a current from the boosted differential signal to provide electrical power to the processing block.

19. The boost device as described in claim 13 , wherein the processing block includes an equalization circuit for equalizing a frequency response of the cable.

20. The boost device as described in claim 13 , wherein the differential output circuit includes means for providing electrical power to the processing block.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2025
From: SPECTRA7 MICROSYSTEMS (IRELAND) LIMITED
To: PARADE TECHNOLOGIES, LTD.
Reel/Frame 071332/0354 →
CHANGE OF NAME Recorded Mar 21, 2025
From: REDMERE TECHNOLOGY LIMITED
To: SPECTRA7 MICROSYSTEMS (IRELAND) LIMITED
Reel/Frame 070582/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 7, 2018
From: SPECTRA 7 MICROSYSTEMS (IRELAND) LIMITED; SPECTRA7 MICROSYSTEMS CORP., AS SUCCESSOR IN INTEREST TO FRESCO MICROCHIP INC.; SPECTRA7 MICROSYSTEMS LTD.
To: MIDCAP FINANCIAL TRUST, AS AGENT
Reel/Frame 047742/0404 →
SECURITY INTEREST Recorded Apr 5, 2016
From: SPECTRA7 MICROSYSTEMS (IRELAND) LIMITED, AS SUCCESSOR IN INTEREST TO REDMERE TECHNOLOGY LIMITED
To: MIDCAP FINANCIAL TRUST, AS AGENT
Reel/Frame 038358/0681 →
RELEASE OF SECURITY INTEREST Recorded Apr 4, 2016
From: COMERICA BANK, A TEXAS BANKING ASSOCIATION AND AUTHORIZED FOREIGN BANK UNDER THE BANK ACT (CANADA)
To: SPECTRA7 MICROSYSTEMS (IRELAND) LIMITED, AS SUCCESSOR IN INTEREST TO REDMERE TECHNOLOGY LIMITED
Reel/Frame 038182/0265 →
SECURITY AGREEMENT Recorded Feb 22, 2013
From: REDMERE TECHNOLOGY LIMITED
To: COMERICA BANK, A TEXAS BANKING ASSOCIATION AND AUTHORIZED FOREIGN BANK UNDER THE BANK ACT (CANADA)
Reel/Frame 029854/0663 →
CHANGE OF ADDRESS Recorded Aug 10, 2011
From: REDMERE TECHNOLOGY LTD.
To: REDMERE TECHNOLOGY LTD.
Reel/Frame 026731/0548 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2009
From: KEADY, AIDAN GERARD; KEANE, JOHN ANTHONY; REA, JUDITH ANN; GRIFFIN, BENJAMIN; HORAN, JOHN MARTIN
To: REDMERE TECHNOLOGY LTD.
Reel/Frame 023077/0088 →
Continuity (4)
Continuation In Part 11826713 · Jul 18, 2007
Provisional Application 60856032 · Nov 2, 2006
Provisional Application 60858353 · Nov 13, 2006
Related Publication 20090289681A1 · Nov 26, 2009