IP Library Granted Patent US 7,910,973
Granted Patent B2
US 7,910,973 · App. 12/404,804 · Granted Mar 22, 2011

Semiconductor storage device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,910,973
App. No.
12/404,804
Granted
Mar 22, 2011
Kind
B2
Abstract

A non-volatile semiconductor storage device has: a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series; and a capacitor element area including capacitor elements. Each of the memory strings includes: a plurality of first conductive layers laminated on a substrate; and a plurality of first interlayer insulation layers formed between the plurality of first conductive layers. The capacitor element area includes: a plurality of second conductive layers laminated on a substrate and formed in the same layer as the first conductive layers; and a plurality of second interlayer insulation layers formed between the plurality of second conductive layers and formed in the same layer as the first interlayer insulation layers. A group of the adjacently-laminated second conductive layers is connected to a first potential, while another group thereof is connected to a second potential.

Claims (73)

1. A semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series, and a capacitor element area including a capacitor element,

each of the memory strings comprising:

a plurality of first conductive layers laminated on a substrate;

a plurality of first interlayer insulation layers formed between the plurality of first conductive layers;

a semiconductor layer formed to penetrate the plurality of first conductive layers and the plurality of first interlayer insulation layers; and

a charge accumulation layer formed between the first conductive layers and the semiconductor layer,

the capacitor element area comprising:

a plurality of second conductive layers laminated on the substrate and formed in the same layer as the first conductive layers; and

a plurality of second interlayer insulation layers formed between the plurality of second conductive layers and formed in the same layer as the first interlayer insulation layers,

a group of the second conductive layers laminated adjacently to form two layers being connected to a first potential,

while another group of the second conductive layers laminated adjacently to form two layers being connected to a second potential different from the first potential, and

the second conductive layers laminated adjacently to form two layers and the second interlayer insulation layer between the second conductive layers configuring the capacitor element.

2. The semiconductor storage device according to claim 1 , comprising:

contact layers formed to be connected to respective ends of the second conductive layers and extend in a lamination direction, wherein

the plurality of first conductive layers and the plurality of second conductive layers are formed in a stepwise manner in relation to each other at their ends, and

the contact layers are connected to the first potential or the second potential.

3. The semiconductor storage device according to claim 1 , wherein

an n+1th second conductive layer from the bottommost one (where n is a natural number not less than 0) is connected to the first potential, and

an n+2th second conductive layer from the bottommost one is connected to the second potential.

4. The semiconductor storage device according to claim 3 , comprising:

contact layers formed to be connected to respective ends of the second conductive layers and extend in a lamination direction, wherein

the plurality of first conductive layers and the plurality of second conductive layers are formed in a stepwise manner in relation to each other at their ends, and

the contact layers are connected to the first potential or the second potential.

5. The semiconductor storage device according to claim 1 , wherein

an 3n+1th second conductive layer from the bottommost one (where n is a natural number not less than 0) is connected to the first potential, and

an 3n+2th and 3n+3th second conductive layers from the bottommost one are connected to the second potential.

6. The semiconductor storage device according to claim 5 , comprising:

contact layers formed to be connected to respective ends of the second conductive layers and extend in a lamination direction, wherein

the plurality of first conductive layers and the plurality of second conductive layers are formed in a stepwise manner in relation to each other at their ends, and

the contact layers are connected to the first potential or the second potential.

7. The semiconductor storage device according to claim 1 , wherein

the first conductive layers and the second conductive layers are formed of the same material, and

the first interlayer insulation layers and the second interlayer insulation layers are formed of the same material.

8. The semiconductor storage device according to claim 1 , wherein

the second conductive layers have the respective ends coincident with those of the second interlayer insulation layers formed on the second conductive layers.

9. A semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series, and a resistor element area including a resistor element,

each of the memory strings comprising:

a plurality of first conductive layers laminated on a substrate;

a plurality of interlayer insulation layers formed between the plurality of first conductive layers;

a semiconductor layer formed to penetrate the plurality of first conductive layers and the plurality of interlayer insulation layers; and

a charge accumulation layer formed between the first conductive layers and the semiconductor layer,

the resistor element area comprising a plurality of second conductive layers laminated on the substrate and formed in the same layer as the first conductive layers, and

at least two layers of the plurality of second conductive layers being connected in series to configure the resistor element.

10. The semiconductor storage device according to claim 9 , comprising:

a plurality of contact layers formed to be connected to ends of the second conductive layers and extend in a lamination direction, wherein

the plurality of first conductive layers and the plurality of second conductive layers are formed in a stepwise manner in relation to each other at their ends, and

the plurality of contact layers are connected to a plurality of upper wiring layers formed on the second conductive layers.

11. The semiconductor storage device according to claim 10 , wherein

an n+1th second conductive layer from the bottommost one (where n is a natural number not less than 0) is connected to a first upper wiring layer and a second upper wiring layer among the upper wiring layers, and

an n+2th second conductive layer from the bottommost one is connected to the second upper wiring layer and a third upper wiring layer among the upper wiring layers.

12. The semiconductor storage device according to claim 9 , wherein

the second conductive layers are formed by the same material as the first conductive layers.

13. The semiconductor storage device according to claim 9 , wherein

the second conductive layers are formed in strip shape.

14. A semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series, and a capacitor/resistor element area including a capacitor element or a resistor element,

each of the memory strings comprising:

a plurality of first conductive layers laminated on a substrate;

a plurality of first interlayer insulation layers formed between the plurality of first conductive layers;

a semiconductor layer formed to penetrate the plurality of first conductive layers and the plurality of first interlayer insulation layers; and

a charge accumulation layer formed between the first conductive layers and the semiconductor layer,

the capacitor/resistor element area comprising:

a plurality of second conductive layers laminated on the substrate and formed in the same layer as the first conductive layers; and

a plurality of second interlayer insulation layers formed between the plurality of second conductive layers and formed in the same layer as the first interlayer insulation layers.

15. The semiconductor storage device according to claim 14 , comprising:

contact layers formed to be connected to respective ends of the second conductive layers and extend in a lamination direction, wherein

the plurality of first conductive layers and the plurality of second conductive layers are formed in a stepwise manner in relation to each other at their ends.

16. The semiconductor storage device according to claim 14 , wherein

the second conductive layers are formed by the same material as the first conductive layers.

17. The semiconductor storage device according to claim 14 , wherein

the first conductive layers and the second conductive layers are formed of the same material, and

the first interlayer insulation layers and the second interlayer insulation layers are formed of the same material.

18. The semiconductor storage device according to claim 14 , wherein

the second conductive layers have the respective ends coincident with those of the second interlayer insulation layers formed on the second conductive layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2009
From: SAKAGUCHI, TAKESHI; NITSUTA, HIROYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 022682/0026 →
Priority Claims (2)
JP 2008-067544 · Mar 17, 2008 · national
JP 2008-068745 · Mar 18, 2008 · national
Continuity (1)
Related Publication 20090230449A1 · Sep 17, 2009