Image sensor monitor structure in scribe area
View Patent ↗A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.
1. A method of monitoring process defects of a complementary metal oxide semiconductor (CMOS) image sensor array, said method comprising:
manufacturing a semiconductor die containing at least one semiconductor chip and at least one test structure, wherein each of said at least one semiconductor chip includes a first array of complementary metal oxide semiconductor (CMOS) image sensors of a type, and wherein each of said at least one test structure includes a second array of complementary metal oxide semiconductor (CMOS) image sensors of said type, and said second array is an m×n array including m×n number of CMOS image sensors of said type, wherein said CMOS image sensors of said type in said first array and said CMOS image sensors of said type in said second array have a same first periodicity along a direction of m repetitions of said m×n array and a same second periodicity along a direction of n repetitions of said m×n array; and
testing said at least one test structure to provide feedback on semiconductor manufacturing processes employed to manufacture said at least one semiconductor chip.
2. The method of claim 1 , further comprising designing said at least one test structure such that said CMOS image sensors in said first array and said CMOS image sensors in said second array have the same orientation.
3. The method of claim 1 , further comprising:
designing said at least one test structure with an empty reserved area for said second array prior to completion of design of said at least one test structure; and
filling said empty reserved area in a design data with said CMOS image sensors prior to manufacture of said semiconductor die.
4. The method of claim 3 , further comprising adjusting orientation of said CMOS image sensors of said second array to match an orientation of said CMOS image sensors of said first array.
5. The method of claim 1 , wherein said first array has a greater number of said CMOS image sensors than said second array.
6. The method of claim 5 , wherein m is a number greater than or equal to 2 and less than or equal to 1024, and wherein n is a number greater than or equal to 2 and less than or equal to 1024.
7. The method of claim 6 , wherein m is a number greater than or equal to 8 and less than or equal to 24, and wherein n is a number greater than or equal to 8 and less than or equal to 24.
8. The method of claim 1 , wherein each of said at least one test structure further comprises:
a set of pads; and
electrical wiring connecting said set of pads and said second array such that said second array is testable through said set of pads.
9. The method of claim 8 , wherein each of said at least one test structure further comprises a peripheral circuitry configured to be connected with a plurality of types of CMOS image sensors.
10. The method of claim 9 , wherein said peripheral circuitry comprises a row decoder, a column decoder, a row driver, column receivers, a column multiplexer, and an operational amplifier (OP-amp).