Method for fabricating semiconductor device having vertical-type channel
A method for fabricating a semiconductor device includes the following steps. A device isolation layer with a trench type is etched in a predetermined portion of a substrate to define an active region. Predetermined portions where gate lines traverse in the device isolation layer are etched to a certain depth to form a plurality of first recesses. A pair of gate lines filling the first recesses and traversing over the active region is formed. Portions of the active region which storage nodes contact on one sides of the gate lines are etched to form a plurality of second recesses. An ion-implantation process is performed to form a plurality of first junction regions beneath the second recesses and to form a second junction region in a portion of the active region between the gate lines such that the second junction region contacts bit lines.
1. A method for fabricating a semiconductor device, comprising:
forming a device isolation layer with a trench type in a predetermined portion of a substrate to define an active region;
etching predetermined portions where gate lines traverse in the device isolation layer to a certain depth to form a plurality of first recesses;
forming a pair of gate lines filling the first recesses and traversing over the active region;
etching portions of the active region which storage nodes contact on one sides of the gate lines to form a plurality of second recesses; and
performing an ion-implantation process to form a plurality of first junction regions beneath the second recesses and to form a second junction region in a portion of the active region between the gate lines, the second junction region contacting bit lines.
2. The method of claim 1 , further comprising forming a plurality of gate spacers on sidewalls of the gate lines.
3. The method of claim 2 , wherein some of the gate spacers are formed on one sidewall of the gate lines over the second junction region, and the remaining gate spacers are formed not only on another sidewall of the gate lines but also on one sidewall of the second recesses.
4. The method of claim 1 , wherein the forming of the first recesses includes:
forming a first photoresist pattern having a plurality of openings exposing portions where the gate lines traverse over the device isolation layer;
selectively etching the device isolation layer exposed beneath the openings by using the first photoresist pattern as an etch mask to form the first recesses; and
removing the first photoresist pattern.
5. The method of claim 4 , wherein the forming of the first recesses is performed by using a gas having high etch selectivity to the active region during etching the device isolation layer.
6. The method of claim 1 , wherein the forming of the second recesses includes:
forming a second photoresist pattern exposing the portion of the active region between the gate lines over the gate lines;
selectively etching the exposed portion of the active region to a predetermined depth by using the second photoresist pattern as an etch mask; and
removing the second photoresist pattern.
7. The method of claim 6 , wherein the forming of the second recesses uses a gas having high etch selectivity to the device isolation layer during etching the exposed portion of the active region.
8. The method of claim 1 , wherein the first junction regions and the second junction region are doped with N-type impurities.