IP Library Granted Patent US 7,924,176
Granted Patent B2
US 7,924,176 · App. 12/827,465 · Granted Apr 12, 2011

N-state ripple adder scheme coding with corresponding N-state ripple adder scheme decoding

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,924,176
App. No.
12/827,465
Granted
Apr 12, 2011
Kind
B2
Abstract

Methods and apparatus for implementing an n-state ripple-adder scheme coder with n≧2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.

Claims (29)

1. An apparatus for enciphering a plurality of n-state symbols with n>2, each n-state symbol assuming one of n states, comprising:

a first device with an input to receive a signal representing a first n-state symbol in the plurality of n-state symbols, the plurality of n-state symbols being processed as a block cipher, and an output for generating a signal representing a transformed first n-state symbol;

a second device with a first input, a second input and an output, the first input enabled to receive a signal representing a second n-state symbol in the plurality of n-state symbols, the second input enabled to receive the signal representing the transformed n-state symbol and the output generating a signal representing an n-state symbol that is generated in accordance with a first reversible n by n n-state truth table, and wherein:

the first reversible n by n n-state truth table is characterized by combining an addition over an n-state Finite Field GF(n) and one or more multiplications over the n-state Finite Field GF(n) not only being a multiplication 1.

2. The apparatus as claimed in claim 1 , wherein the first reversible n by n n-state truth table cannot characterized by exclusively using an addition over an n-state Finite Field GF(n) and a multiplication over the n-state Finite Field GF(n).

3. The apparatus as claimed in claim 1 , wherein the first device has a second input enabled to receive a signal representing a key.

4. The apparatus as claimed in claim 1 , wherein the first n-state symbol has been generated in a first path of a previous enciphering round and the second n-state symbol has been generated in a second path of a previous enciphering round.

5. The apparatus as claimed in claim 1 , further comprising a corresponding deciphering apparatus for recovering the first n-state symbol from an enciphered n-state symbol.

6. The apparatus as claimed in claim 1 , wherein the second device implements a reversible n-state ripple adder coder.

7. The apparatus as claimed in claim 1 , wherein the apparatus includes a Feistel network.

8. The apparatus as claimed in claim 1 , wherein the first n by n reversible n-state truth table is replaced by an implementation of a second n by n reversible n-state truth table after processing the second n-state symbol.

9. The apparatus as claimed in claim 1 , wherein an n-state symbol is represented by one or more binary signals.

10. The apparatus as claimed in claim 1 , wherein the transformed first n-state symbol is generated in a non-reversible manner.

11. A system for enciphering a plurality of n-state symbols including a first n-state symbol and a second n-state symbol with n>2, each n-state symbol assuming one of n states, comprising:

a processor with a memory, the memory enabled to store instructions, the processor retrieving the instructions from the memory and executing the instruction on one or more signals representing the plurality of n-state symbols wherein the plurality of n-state symbols is being processed as part of a block cipher, to perform the steps of:

transforming a signal representing the first n-state symbol in the plurality of n-state symbols into a signal representing a transformed first n-state symbol; and

processing a signal representing the second n-state symbol and the signal representing the transformed first n-state symbol to generate a signal representing an enciphered n-state symbol in accordance with a first reversible n by n truth table that cannot be characterized by exclusively using an addition over an n-state Finite Field and a multiplication over the n-state Finite Field.

12. The system as claimed in claim 11 , wherein the transformed first n-state symbol is generated by applying a key.

13. The system as claimed in claim 11 , wherein the first n-state symbol is generated in a first path of a previous enciphering round and the second n-state symbol is generated in a second path of a previous enciphering round.

14. The system as claimed in claim 11 , further comprising a deciphering apparatus for recovering the first n-state symbol from an enciphered n-state symbol.

15. The system as claimed in claim 11 , wherein the system includes a Feistel network.

16. The system as claimed in claim 11 , wherein the first reversible n by n n-state truth table is replaced by an implementation of a second reversible n by n n-state truth table after processing the second n-state symbol.

17. The system as claimed in claim 11 , wherein an n-state symbol is represented by one or more binary signals.

18. The system as claimed in claim 11 , wherein the system is part of a financial system.

19. A method for enciphering a plurality of n-state symbols with n>2, each n-state symbol being represented by a signal, comprising:

processing a plurality of signals representing the n-state symbols as a block cipher by a processor, including the steps of:

transforming a signal representing the first n-state symbol in the plurality of n-state symbols, into a signal representing a transformed first n-state symbol; and

processing a signal representing the second n-state symbol and the signal representing the transformed first n-state signal by the processor to generate a signal representing an enciphered n-state symbol in accordance with a first reversible n by n truth table that cannot be characterized by exclusively using an addition over an n-state Finite Field GF(n) and a multiplication over the n-state Finite Field GF(n).

20. The method as claimed in claim 19 , further comprising a method for deciphering the enciphered n-state symbol.

Continuity (3)
Continuation 12330255 · Dec 8, 2008
Provisional Application 61012548 · Dec 10, 2007
Related Publication 20100271243A1 · Oct 28, 2010