IP Library Granted Patent US 7,928,794
Granted Patent B2
US 7,928,794 · App. 12/176,769 · Granted Apr 19, 2011

Method and apparatus for a dynamically self-bootstrapped switch

Assignee: Analog Devices, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,928,794
App. No.
12/176,769
Granted
Apr 19, 2011
Kind
B2
Abstract

A dynamically self-bootstrapping circuit for a switch features a resistor in series with the control node of the switch. A bypass switch connects a control node to ground. When the switch is in an off-state, the bypass switch is enabled.

Claims (36)

1. A dynamically self-bootstrapping circuit for a switch comprising:

a first resistor connecting a control node of the switch to a switch control input;

a first bypass switch connecting the control node of the switch to ground;

a first bypass switch resistor in series with a gate node of the first bypass switch; and

a second bypass switch resistor in series with a back gate node of the first bypass switch, the first and second bypass switch resistors self-bootstrapping the first bypass switch,

wherein the first bypass switch is disabled when the switch is in an on-state and enabled when the switch is in an off-state.

2. The circuit of claim 1 , wherein the switch is an FET switch and the control node is a gate node of the FET switch.

3. The circuit of claim 2 , further comprising:

a second resistor connecting a back gate node of the FET switch to ground; and

a second bypass switch connecting the back gate node of the FET switch to ground,

wherein the second bypass switch is disabled when the FET switch is in an on-state, and enabled when the FET switch is in an off-state.

4. The circuit of claim 3 , further comprising:

a third bypass switch resistor in series with a gate node of the second bypass switch; and

a fourth bypass switch resistor in series with a back gate node of the second bypass switch, the third and fourth bypass switch resistors self-bootstrapping the second bypass switch.

5. The circuit of claim 2 , wherein the FET switch is a pass-gate switch.

6. The circuit of claim 5 , wherein the pass-gate switch is selected from the group consisting of an NMOS transistor, a PMOS transistor, and an NMOS transistor in parallel with a PMOS transistor.

7. The circuit of claim 2 , wherein the FET switch is an RF switch.

8. The circuit of claim 7 , wherein the RF switch is selected from the group consisting of a transmit/receive switch, a switched attenuator, multipole/multithrow (MPMT) switches, and a capacitor band-switched VCO.

9. The circuit of claim 1 , wherein the switch comprises a plurality of cascaded transistors.

10. The circuit of claim 1 , wherein the switch is a MEMS switch.

11. A method of dynamically self-bootstrapping a switch comprising:

connecting a first resistor between a control node of the switch and a switch control input;

allowing a voltage on the control node to track an input signal voltage when the switch is in an on-state;

preventing the voltage on the control node from tracking the input signal voltage when the switch is in an off-state by bypassing the first resistor with a first bypass switch; and

self-bootstrapping the first bypass switch with a first bypass switch resistor in series with a gate node of the first bypass switch and a second bypass switch resistor in series with a back gate node of the first bypass switch.

12. The method of claim 11 , wherein the switch is a FET switch and the control node is a gate node of the FET switch.

13. The method of claim 12 , further comprising:

connecting a second resistor between a back gate node of the FET switch and ground; and

bypassing the second resistor with a second bypass switch when the FET switch is in an off-state.

14. The method of claim 13 , further comprising self-bootstrapping the second bypass switch with a third bypass switch resistor in series with a gate node of the second bypass switch and a fourth bypass switch resistor in series with a back gate node of the second bypass switch.

15. The method of claim 12 , wherein the FET switch is a pass-gate switch.

16. The method of claim 15 , wherein the pass-gate switch is selected from the group consisting of an NMOS transistor, a PMOS transistor, and an NMOS transistor in parallel with a PMOS transistor.

17. The method of claim 12 , wherein the FET switch is an RF switch.

18. The method of claim 17 , wherein the RF switch is selected from .the group consisting of a transmit/receive switch, a switched attenuator, multipole/multithrow (MPMT) switches, and a capacitor band-switched VCO.

19. The method of claim 11 , wherein the switch comprises a plurality of cascaded transistors.

20. The method of claim 11 , wherein the switch is a MEMS switch.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2011
From: BALBONI, EDMUND J
To: ANALOG DEVICES, INC.
Reel/Frame 025968/0731 →
Continuity (1)
Related Publication 20100013541A1 · Jan 21, 2010