High-speed verifiable semiconductor memory device
A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.
1. A semiconductor memory device comprising:
a memory cell array having a plurality of memory cells, each of the memory cells being connected to a word line, a bit line and a source line and storing a plurality of bits by setting the word line to one of a first level, a second level, and an nth level (n: natural number more than 3); and
first and second select gates, each of the memory cells being connected to the bit line and the source line by the first and second select gates, respectively,
wherein when data is read from a memory cell, the bit line is precharged and the word line is set to i level (i: voluntary level of n) and then, the first and/or second select gates are turned on, data of the memory cell is read by i level;
then the first and second select gates are turned off, the word line is set to j level (j: voluntary level of n, j≠i) and, then the first and/or second select gates are turned on, data of the memory cell is read by j level.
2. A semiconductor memory device comprising:
a memory cell array having a plurality of memory cells arrayed like a matrix, each of the memory cells being connected to a word line, a bit line and a source line and storing n levels (n: natural number more than 3);
first and second select gates, each of the memory cells being connected to the bit line and the source line by the first and second select gates, respectively; and
a control circuit configured to write data into each of the memory cells by controlling each potential of the word line and the bit line in accordance with input data,
wherein the control circuit writes a threshold voltage of k level (k<=n) to a memory cell in the write operation, and charge the bit line, thereafter, charge the word line potential to level of n level (i<=k), the first and second select gates are turned on to verify whether or not level of the memory cell reaches i level, after the first and second select gates are turned off, charge the word line potential to j level (j<=k), then the first and/or second select gates are turned on to verify whether or not level of the memory cell reaches j level.
3. The device according to claim 1 , wherein the memory cells are arranged in rows and the memory cells in each row are connected in series and the first and second select gates are connected to each of ends of the memory cells connected in series.
4. The device according to claim 2 , wherein the memory cells are arranged in rows and the memory cells in each row are connected in series and the first and second select gates are connected to each of ends of the memory cells connected in series.