Device and method for controlling multiple DMA tasks
A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting. A device that includes a memory unit; the device is characterized by including a DMA controller that is adapted to: (i) access at least one buffer descriptor out of multiple buffer descriptors defined for each of a plurality of DMA channel, wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; (ii) receive multiple DMA task requests, (iii) select a DMA task request out of the multiple DMA task requests, and (iv) execute a DMA task or a DMA task iteration and update a buffer descriptor associated with the selected DMA task request to reflect the execution.
1. A method for controlling multiple DMA tasks, the method comprises:
receiving multiple DMA task requests;
defining multiple buffer descriptors for each of a plurality of DMA channels wherein at least two buffer descriptors comprise timing information that control an execution of cyclic time based DMA tasks;
selecting a DMA task request out of the multiple DMA task requests;
executing a DMA task or a DMA task iteration using different I/O ports during different DMA task iterations, and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and
jumping to the stage of selecting.
2. The method according to claim 1 wherein at least one buffer descriptor is stored in a memory unit that is coupled to a DMA controller and wherein an execution of a first iteration of a cyclic time based DMA task comprises retrieving a buffer descriptor associated with the cyclic time based DMA task from the memory unit.
3. The method according to claim 2 , wherein the timing information defines a DMA task execution interval and a DMA task priority.
4. The method according to claim 2 , wherein at least one buffer descriptor comprises a current iteration I/O port selection information and a next iteration I/O port selection information.
5. The method according to claim 2 , wherein at least one buffer descriptor comprises arbitration type information.
6. The method according to claim 2 , wherein at least one cyclic time based DMA tasks comprises multiple DMA sub tasks associated with multidimensional buffers.
7. The method according to claim 1 , wherein the timing information defines a DMA task execution interval and a DMA task priority.
8. The method according to claim 1 , wherein at least one buffer descriptor comprises a current iteration I/O port selection information and a next iteration I/O port selection information.
9. The method according to claim 1 , wherein at least one buffer descriptor comprises arbitration type information.
10. The method according to claim 1 , wherein at least one cyclic time based DMA tasks comprises multiple DMA sub tasks associated with multidimensional buffers.
11. The method according to claim 1 , further comprising generating an interrupt request once a possible timing violation is detected.
12. A device comprising:
a memory unit;
a DMA controller comprising multiple I/O ports, wherein the DMA controller is adapted to:
(i) access at least one buffer descriptor out of multiple buffer descriptors defined for each of a plurality of DMA channels, wherein at least two buffer descriptors comprise timing information that control an execution of cyclic time based DMA tasks;
(ii) receive multiple DMA task requests,
(iii) select a DMA task request out of the multiple DMA task requests; and
(iv) execute a DMA task or a DMA task iteration using different I/O ports during different DMA task iterations, and update a buffer descriptor associated with the selected DMA task request to reflect the execution.
13. The device according to claim 12 wherein at least one buffer descriptor is stored in a memory unit that is coupled to a DMA controller, and wherein an execution of a first iteration of a cyclic time based DMA task comprises a retrieval of a buffer descriptor associated with the cyclic time based DMA task from the memory unit.
14. The device according to claim 12 , wherein the timing information defines a DMA task execution interval and a DMA task priority.
15. The device according to claim 12 , wherein at least one buffer descriptor comprises a current iteration I/O port selection information and a next iteration I/O port selection information.
16. The device according to claim 12 , wherein at least one buffer descriptor comprises arbitration type information.
17. The device according to claim 12 , wherein at least one cyclic time based DMA tasks comprises multiple DMA sub tasks associated with multidimensional buffers.
18. The device according to claim 12 , wherein the DMA controller is adapted to generate an interrupt request once a possible timing violation is detected.
19. A method for controlling multiple DMA tasks, the method comprises:
receiving multiple DMA task requests;
defining multiple buffer descriptors for each of a plurality of DMA channels wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks, wherein a first of the at least two descriptors defines a DMA task execution interval and a second of the at least two descriptors defines a DMA task priority;
selecting a DMA task request out of the multiple DMA task requests;
executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and
jumping to the stage of selecting.
20. The method of claim 19 , further comprising utilizing different I/O ports during different DMA task iterations.