IP Library Granted Patent US 7,944,751
Granted Patent B2
US 7,944,751 · App. 12/556,970 · Granted May 17, 2011

Method for programming of memory cells, in particular of the flash type, and corresponding programming architecture

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Quick Facts
Patent No.
US 7,944,751
App. No.
12/556,970
Granted
May 17, 2011
Kind
B2
Abstract

A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.

Claims (39)

1. A method for programming Flash memory cells comprising:

programming a group of memory cells;

identifying cells within the group that need to be programmed again;

determining a number of cells to be reprogrammed at one time based on the driving capacity of a charge pump for programming said cells;

storing the number of memory cells to be reprogrammed;

grouping the cells according to the relation:

n=I charge_pump/ I cell

wherein:

Icharge_pump is a maximum value of the current which can be supplied by the charge pump, and

Icell is a value of current absorbed by a memory cell during a programming; and

generating a control flag PR_PAGE according to the relation:

PR_PAGE=1 if the number of memory cells to be programmed is lower or equal to the second parallelism; and

PR_PAGE=0 if the number of memory cells to be programmed is higher than the second parallelism;

if PR_PAGE=1, attribution to the programming parallelism of a value corresponding to a value of maximum parallelism; and

if PR_PAGE=0 attribution to the programming parallelism of a value corresponding to a value of minimum parallelism.

2. The programming method of claim 1 , wherein the value of maximum parallelism corresponds to the first parallelism.

3. The programming method of claim 1 , wherein the value of minimum parallelism corresponds to the second parallelism.

4. The programming method of claim 1 , further comprising a determination step of a number of programming pulses according to the relation:

bit_to — pr/n =number of pulses,

the number of pulses being an integer number and the programming step comprising the number of pulses.

5. The programming method of claim 1 , including:

if the number of memory cells to be programmed is higher than the second parallelism (bit_to_pr>n), attributing to the programming parallelism of a value corresponding to half of the value of maximum parallelism (np=M/2);

this relation being consecutively applied up to the exhaustion of the cells to be programmed.

6. The programming method of claim 1 , further comprising storage of a second parallelism indicative of a driving capability of a charge pump for generation of a programming voltage of the cells and a setting step of the second parallelism.

7. The programming method of claim 1 , further comprising storage of a second parallelism indicative of a driving capability of a charge pump for generation of a programming voltage of the cells and a calculation step of the second parallelism by means of comparison of a value of the current absorbed by the memory cells during a programming and/or soft-programming step with a value of reference current.

8. A method for programming Flash memory cells comprising:

programming a group of memory cells;

identifying cells within the group that need to be programmed again;

determining a number of cells to be reprogrammed at one time based on the driving capacity of a charge pump for programming said cells;

including storing the number of memory cells to be reprogrammed;

further comprising:

grouping of the cells according to the relation:

n=I charge_pump/ I cell

wherein:

Icharge_pump is a maximum value of the current which can be supplied by the charge pump, and

Icell is a value of current absorbed by a memory cell during a programming; and

further comprising a determination step of a number of programming pulses according to the relation:

number of cells to be programmed divided by n=number of pulses,

the number of pulses being an integer number and the programming step comprising the number of pulses.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →