Frequency counter based analog-to-digital converter
View Patent ↗An analog-to-digital converter (ADC) is provided. The ADC includes a variable oscillator, a frequency divider, a clock circuit, and a counter. The variable oscillator is coupled to a sensor and configured to generate an oscillating signal based on a measurement generated by the sensor. The frequency divider is coupled to the variable oscillator and configured to divide a frequency of the oscillating signal. The clock circuit is configured to generate a clock signal at a defined frequency. The counter is coupled to the frequency divider and to the clock and is configured to generate a bit stream representative of a first number of periods of the clock signal during a second number of periods of the divided oscillating signal.
1. An analog-to-digital converter comprising:
a variable oscillator coupled to a sensor and configured to generate an oscillating signal based on a measurement generated by the sensor;
a frequency divider coupled to the variable oscillator and configured to divide a frequency of the oscillating signal;
a clock circuit configured to generate a clock signal at a defined frequency, wherein the clock signal is at a carrier frequency of a radio frequency identifier system; and
a counter coupled to the frequency divider and to the clock and configured to generate a bit stream representative of a first number of periods of the clock signal during a second number of periods of the divided oscillating signal.
2. The analog-to-digital converter of claim 1 , wherein the second number of periods is one.
3. The analog-to-digital converter of claim 1 , wherein the counter comprises a plurality of shift registers configured to generate the bit stream, wherein the bit stream comprises a specific number of bits based on a number of the plurality of shift registers.
4. The analog-to-digital converter of claim 1 , wherein the variable oscillator is a multivibrator.
5. The analog-to-digital converter of claim 1 , wherein the clock circuit is a clock recovery circuit configured to convert a carrier signal to a square wave signal.
6. A device comprising:
a sensor; and
an analog-to-digital converter comprising
a variable oscillator coupled to the sensor and configured to generate an oscillating signal based on a measurement generated by the sensor;
a frequency divider coupled to the variable oscillator and configured to divide a frequency of the oscillating signal;
a clock circuit configured to generate a clock signal at a defined frequency, wherein the clock signal is at a carrier frequency of a radio frequency identifier system; and
a counter coupled to the frequency divider and to the clock and configured to generate a bit stream representative of a first number of periods of the clock signal during a second number of periods of the divided oscillating signal.
7. The device of claim 6 , wherein the sensor is a capacitive or a resistive sensing element.
8. The device of claim 6 , further comprising a coil coupled to receive the bit stream and generate a magnetic and/or an electric field based on the received bit stream.
9. The device of claim 6 , wherein the clock circuit is a clock recovery circuit configured to convert a carrier signal to a square wave signal.
10. The device of claim 6 , further comprising a modulator circuit coupled to receive the generated bit stream and coupled to receive a first frequency signal at a first frequency from the frequency divider and to receive a second frequency signal at a second frequency different from the first frequency from the frequency divider.
11. The device of claim 10 , wherein the first frequency and the second frequency are the highest two frequencies generated from the frequency divider.
12. The device of claim 10 , wherein the modulator circuit is configured to encode the received bit stream at the first frequency for a logic high bit value and at the second frequency for a logic low bit value.
13. The device of claim 6 , further comprising an enable/reset circuit coupled to the analog-to-digital converter and configured to provide a signal enabling operation of the analog-to-digital converter.
14. The device of claim 13 , further comprising a turn-on/brown-out circuit coupled to the enable/reset circuit and configured to provide a signal to the enable/reset circuit indicating a full power supply voltage.
15. The device of claim 6 , further comprising a cyclic redundancy check generator coupled to the analog-to-digital converter and configured to receive the generated bit stream and generate a checkword based on the received bit stream.
16. The device of claim 15 , wherein the cyclic redundancy check generator is further configured to append the generated checkword to the received bit stream.
17. A telemetry system comprising:
a first device comprising
a sensor;
an analog-to-digital converter comprising
a variable oscillator coupled to the sensor and configured to generate an oscillating signal based on a measurement generated by the sensor;
a frequency divider coupled to the variable oscillator and configured to divide a frequency of the oscillating signal;
a clock circuit configured to generate a clock signal at a defined frequency; and
a counter coupled to the frequency divider and to the clock and configured to generate a bit stream representative of a first number of periods of the clock signal during a second number of periods of the divided oscillating signal; and
a first coil coupled to receive the bit stream and generate a magnetic and/or an electric field based on the received bit stream; and
a second device comprising
a second coil configured to receive the generated magnetic and/or electric field; and
a signal processor configured to determine the measurement generated by the sensor from the received magnetic and/or electric field.
18. The telemetry system of claim 17 , wherein the clock circuit is a clock recovery circuit configured to convert a carrier signal to a square wave signal.