IP Library Granted Patent US 7,958,298
Granted Patent B2
US 7,958,298 · App. 12/079,260 · Granted Jun 7, 2011

System and method for providing address decode and virtual function (VF) migration support in a peripheral component interconnect express (PCIE) multi-root input/output virtualization (IOV) environment

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 7,958,298
App. No.
12/079,260
Granted
Jun 7, 2011
Kind
B2
Abstract

The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value. The method may further include constructing a requestor ID for the VF associated with the matching base address value, the requestor ID being based upon the output matching base address value and a bus number for a PF which owns the CAM.

Claims (41)

1. A method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment, comprising:

receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment;

comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF);

when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value; and

constructing a requestor ID for the VF associated with the matching base address value, the requestor ID being based upon the output matching base address value and a bus number for a PF which owns the CAM.

2. A method as claimed in claim 1 , further comprising:

providing the requestor ID to the PCIE multi-root IOV environment via a completion packet.

3. A method as claimed in claim 2 , further comprising:

receiving a CAM update request from the PCIE multi-root IOV environment.

4. A method as claimed in claim 3 , further comprising:

determining if an update of the CAM is required.

5. A method as claimed in claim 4 , further comprising:

when it is determined that an update of the CAM is required, writing new base address values to the CAM.

6. A method as claimed in claim 5 , further comprising:

receiving a VF migration request from the PCIE IOV environment.

7. A method as claimed in claim 6 , further comprising:

mapping an unmapped Logical Virtual Function (LVF) to a Mission Virtual Function (MVF).

8. A method as claimed in claim 7 , further comprising:

enabling base address decoding for a VF which has undergone a migrate-in event.

9. A method as claimed in claim 8 , further comprising:

accessing base address values for the VF which has undergone the migrate-in event from a configuration space of the PCIE multi-root IOV environment.

10. A method as claimed in claim 9 , further comprising:

updating the CAM by writing the base address values to the CAM for the VF which has undergone the migrate-in event.

11. A non-transitory computer-readable medium having computer-executable instructions for performing a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment, said method comprising: receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment; comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF); when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value; and constructing a requestor ID for the VF associated with the matching base address value, the requestor ID being based upon the output matching base address value and a bus number for a PF which owns the CAM.

12. A computer-readable medium as claimed in claim 11 , said method further comprising:

providing the requestor ID to the PCIE multi-root IOV environment via a completion packet.

13. A computer-readable medium as claimed in claim 12 , said method further comprising:

receiving a CAM update request from the PCIE multi-root IOV environment.

14. A computer-readable medium as claimed in claim 13 , said method further comprising:

determining if an update of the CAM is required.

15. A computer-readable medium as claimed in claim 14 , said method further comprising:

when it is determined that an update of the CAM is required, writing new base address values to the CAM.

16. A computer-readable medium as claimed in claim 15 , said method further comprising:

receiving a VF migration request from the PCIE IOV environment.

17. A computer-readable medium as claimed in claim 16 , said method further comprising:

mapping an unmapped Logical Virtual Function (LVF) to a Mission Virtual Function (MVF); and

enabling base address decoding for a VF which has undergone a migrate-in event.

18. A computer-readable medium as claimed in claim 17 , said method further comprising:

accessing base address values for the VF which has undergone the migrate-in event from a configuration space of the PCIE multi-root IOV environment.

19. A computer-readable medium as claimed in claim 18 , said method further comprising:

updating the CAM by writing the base address values to the CAM for the VF which has undergone the migrate-in event.

Assignments (11)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
RE-RECORD TO CORRECT A DOCUMENT PREVIOUSLY RECORDED AT REEL 021270, FRAME 0992. (ASSIGNMENT OF ASSIGNOR'S INTEREST) Recorded Aug 7, 2008
From: DESHPANDE, VENKATESH; HALDAR, ANIRUDDHA; KOTTEKKAT, SUJIL
To: LSI CORPORATION
Reel/Frame 021355/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2008
From: DESHPANDE, VENKATESH; HALDAR, ANIRUDAHA; KOTTEKKAT, SUJIL
To: LSI COPORATION
Reel/Frame 021270/0992 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2008
From: DESHPANDE, VENKATESH; HALDAR, ANIRUDH; KOTTEKKAT, SUJIL
To: LSI CORPORATION
Reel/Frame 020894/0747 →
Continuity (1)
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