Address window support for direct memory access translation
An apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit of the apparatus includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.
1. A computer hardware apparatus to receive a direct memory access (DMA) request from an input/output (IO) device, the computer hardware apparatus comprising:
an input/output memory management unit (IOMMU) coupled to a Virtual Machine Monitor (VMM), the IOMMU including:
a hardware DMA remapping circuit to:
assign the IO device to a specific guest virtual machine (VM) domain; and
provide an address translation for the DMA request via a DMA remapping structure including an address window (AW), address window page tables (AWPTs), and an address window pointer table (AWPTR) associated with the specific guest VM domain;
an input/output translation lookaside buffer (IOTLB) to cache the address translation associated with the specific guest virtual machine domain;
a logic to determine from the access request whether the address translation for the access request exists in the IOTLB; and
a context-cache for further determining the address translation if the logic determined the access request is non-existent in the IOTLB,
wherein the hardware DMA remapping circuit to provide the address translation for the DMA request based, at least in part, on the AWPTs and the IOTLB, and based on determining whether the address translation exists in the IOTLB, and wherein the hardware DMA remapping circuit to provide the address translation for the DMA request for the address of the IO device to be directly mapped to a respective guest VM via the hardware DMA remapping circuit.
2. The computer hardware apparatus of claim 1 , wherein the address translation comprises a translation from a guest physical address (GPA) to a host physical address (HPA).
3. The computer hardware apparatus of claim 1 , wherein the IO device is uniquely identifiable through a combination of a bus number, a device number, and a function number.
4. The computer hardware apparatus of claim 1 , wherein the hardware DMA remapping circuit includes a register set to provide control or status information to a storage unit.
5. The computer hardware apparatus of claim 1 , wherein the hardware DMA remapping circuit is operable, independent of trapping to the VMM, to directly map the IO device to the specific VM domain by running a driver of the IO device only in the VM.
6. The computer hardware apparatus of claim 1 further comprises a second hardware DMA remapping circuit to perform independently of the other hardware DMA remapping circuit.
7. The computer hardware apparatus of claim 1 further comprises an IO controller to receive the DMA request from the IO device, wherein the IOMMU is coupled to the IO controller.
8. The computer hardware apparatus of claim 1 , wherein the hardware DMA remapping circuit is operable to process the DMA request if the translation is to be blocked pr processed through single-level or multi-level page-tables.