IP Library Granted Patent US 7,994,852
Granted Patent B2
US 7,994,852 · App. 12/619,923 · Granted Aug 9, 2011

Electronic circuit and electronic device

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 7,994,852
App. No.
12/619,923
Granted
Aug 9, 2011
Kind
B2
Abstract

An electronic circuit includes: a circuit generating first and second balanced differential input signals; a first envelope detection circuit including a first output terminal and first and second input terminals receiving the first and second input signals, respectively, via first and second impedance elements, respectively, and outputs from the first output terminal a first output signal that is the sum of the squares of the first and second input signals; a second envelope detection circuit including a second output terminal and third and fourth input terminals receiving the first and second input signals, respectively, via third and fourth impedance elements, respectively, and outputs from the second output terminal a second output signal that is twice the value obtained by squaring the average of the first and second input signals; and a differential circuit generating a differential signal from the first and second output signals.

Claims (27)

1. An electronic circuit comprising:

a circuit that generates a first input signal and a second input signal that are balanced differential signals;

a first envelope detection circuit that includes a first input terminal, a second input terminal, and a first output terminal, the first input signal being input to the first input terminal via a first impedance element, the second input signal being input to the second input terminal via a second impedance element, and outputs from the first output terminal a first output signal that is a sum of the square of the first input signal and the square of the second input signal;

a second envelope detection circuit that includes a third input terminal, a fourth input terminal, and a second output terminal, the first input signal being input to the third input terminal via a third impedance element, the second input signal being input to the fourth input terminal via a fourth impedance element, and outputs from the second output terminal a second output signal that is twice a value obtained by squaring the average of the first input signal and the second input signal; and

a differential circuit that generates a differential signal from the first output signal and the second output signal.

2. The electronic circuit according to claim 1 , wherein

the first envelope detection circuit and the second envelope detection circuit have characteristics equal to each other, and

each includes a first field effect transistor to whose gate terminal the first input signal is input and whose source terminal is connected to a first potential line,

a second field effect transistor to whose gate terminal the second input signal is input and whose source terminal is connected to the first potential line,

a third field effect transistor whose source terminal is connected to a drain terminal of the first field effect transistor and whose gate terminal is biased to a predetermined potential,

a fourth field effect transistor whose source terminal is connected to the drain terminal of the second field effect transistor and whose gate terminal is biased to the predetermined potential, and

an output line that connects the drain terminal of the third field effect transistor with the drain terminal of the fourth field effect transistor to output an output signal, and

the second envelope detection circuit is short-circuited between the third input terminal and the fourth input terminal through a short-circuit line.

3. An electronic device comprising an electronic circuit according to claim 1 .

4. The electronic device according to claim 3 , further comprising a signal processing section that detects pulses carried by a supplied UWB signal.

5. The electronic device according to claim 4 , further comprising a circuit portion to which power is supplied only when a UWB signal is present in at least a part thereof, and a switch circuit therefor.

6. An electronic circuit comprising:

a circuit that generates a first input signal and a second input signal that are balanced differential signals;

a first amplifier circuit that includes a first input terminal, a second input terminal, and a first output terminal, the first input signal being input to the first input terminal via a first impedance element, the second input signal being input to the second input terminal via a second impedance element, and outputs from the first output terminal a first output signal that is obtained by comparing the first input signal and the second input signal to select the larger one and amplifying the selected signal;

a second amplifier circuit that includes a third input terminal, a fourth input terminal, and a second output terminal, the first input signal being input to the third input terminal via a third impedance element, the second input signal being input to the fourth input terminal via a fourth impedance element, outputs from the second output terminal a second output signal that is obtained by amplifying the average of the first input signal and the second input signal, and has characteristics equal to those of the first amplifier circuit; and

a differential circuit that generates a differential signal from the first output signal and the second output signal.

7. The electronic circuit according to claim 6 , wherein

the first amplifier circuit and the second amplifier circuit have characteristics equal to each other, and

each includes a first field effect transistor to whose gate terminal the first input signal is input and whose drain terminal is connected to a first potential line,

a second field effect transistor to whose gate terminal the second input signal is input and whose drain terminal is connected to the first potential line, and

an output line that connects the source terminal of the first field effect transistor with the source terminal of the second field effect transistor to output an output signal, and

the second amplifier circuit is short-circuited between the third input terminal and the fourth input terminal through a short-circuit line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2019
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 050197/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2009
From: IKEDA, MASAYUKI
To: SEIKO EPSON CORPORATION
Reel/Frame 023528/0542 →
Priority Claims (1)
JP 2008-300526 · Nov 26, 2008 · national
Continuity (1)
Related Publication 20100127770A1 · May 27, 2010