IP Library Granted Patent US 8,003,525
Granted Patent B2
US 8,003,525 · App. 12/146,946 · Granted Aug 23, 2011

Semiconductor device and method of manufacturing the same

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 8,003,525
App. No.
12/146,946
Granted
Aug 23, 2011
Kind
B2
Abstract

A GaN layer and an n-type AlGaN layer are formed over an insulating substrate, and thereafter, a gate electrode, a source electrode and a drain electrode are formed on them. Next, an opening reaching at least a surface of the insulating substrate is formed in the source electrode, the GaN layer and the n-type AlGaN layer. Then, a nickel (Ni) layer is formed in the opening. Thereafter, by conducting dry etching from the back side while making the nickel (Ni) layer serve as an etching stopper, a via hole reaching the nickel (Ni) layer is formed in the insulating substrate. Then, a via wiring is formed extending from an inside the via hole to the back surface of the insulating substrate.

Claims (30)

1. A method of manufacturing a semiconductor device, comprising:

forming a compound semiconductor layer over a substrate;

forming a gate electrode, a source electrode and a drain electrode on said compound semiconductor layer;

forming a passivation film covering said gate electrode, said source electrode and said drain electrode;

forming an opening penetrating said passivation film and reaching at least a surface of said substrate in said compound semiconductor layer;

forming a first metal layer containing tantalum (Ta) or tantalum nitride (TaN) in said opening;

forming a conductive layer coupled to said source electrode on said first metal layer in said opening;

conducting dry etching from a back side of said substrate while making said conductive layer serve as an etching stopper so as to form a via hole reaching said conductive layer; and

forming a via wiring extending from an inside of said via hole to a back surface of said substrate.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein a gas containing fluorine is used in conducting said dry etching.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein forming said opening comprises etching said compound semiconductor layer using a gas containing chlorine.

4. The method of manufacturing a semiconductor device according to claim 1 , wherein said conductive layer contains nickel (Ni).

5. The method of manufacturing a semiconductor device according to claim 1 , wherein said substrate contains silicon carbide (SiC).

6. The method of manufacturing a semiconductor device according to claim 1 , further comprising, between forming said conductive layer and forming said via hole, forming a metal mask on the back surface of said substrate.

7. The method of manufacturing a semiconductor device according to claim 6 , wherein said metal mask contains nickel (Ni).

8. The method of manufacturing a semiconductor device according to claim 6 , further comprising, before forming said metal mask, forming a second metal layer on the back surface of said substrate,

wherein said metal mask is formed over said second metal layer.

9. The method of manufacturing a semiconductor device according to claim 8 , wherein said second metal layer contains metal having a melting point higher than titanium (Ti).

10. A method of manufacturing a semiconductor device, comprising:

forming a compound semiconductor layer over an insulating substrate;

forming a gate electrode, a source electrode and a drain electrode on said compound semiconductor layer;

forming a passivation film covering said gate electrode, said source electrode and said drain electrode;

forming an opening penetrating said passivation film and reaching at least a surface of said insulating substrate in said source electrode and said compound semiconductor layer;

forming a first metal layer containing tantalum (Ta) or tantalum nitride (TaN) in said opening;

forming a conductive layer on said first metal layer in said opening;

conducting dry etching from a back side of said insulating substrate while making said conductive layer serve as an etching stopper so as to form a via hole reaching said conductive layer; and

forming a via wiring extending from an inside of said via hole to a back surface of said insulating substrate.

11. The method of manufacturing a semiconductor device according to claim 10 , wherein a gas containing fluorine is used in conducting said dry etching.

12. The method of manufacturing a semiconductor device according to claim 10 , further comprising, between forming said conductive layer and forming said via hole, forming a metal mask on the back of said insulating substrate.

13. The method of manufacturing a semiconductor device according to claim 10 , wherein forming said via wiring comprises forming a copper (Cu) layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2008
From: OKAMOTO, NAOYA
To: FUJITSU LIMITED
Reel/Frame 021161/0623 →
Priority Claims (2)
JP 2007-172345 · Jun 29, 2007 · national
JP 2008-034974 · Feb 15, 2008 · national
Continuity (1)
Related Publication 20090001478A1 · Jan 1, 2009