Static-dynamic-dynamic repeater circuit

1. An electronic circuit comprising:

an input stage coupled to an input node and including a first input circuit and a second input circuit;

an intermediate stage including a first intermediate circuit and a second intermediate circuit;

an output stage including a first output circuit and a second output circuit each coupled to an output node and configured to drive the output node, when active; and

a feedback path, wherein a first node of the feedback path is the output node and wherein a second node of the feedback path is coupled to the intermediate stage;

wherein, responsive to a transition from a first logic level to a second logic level of an input signal on the input node, the first input circuit is configured to activate the first intermediate circuit and wherein, responsive thereto, the first intermediate circuit is configured to activate the first output circuit, wherein, the first output circuit is configured to, when activated, drive an output signal on the output node, and

wherein, after a delay, the first intermediate and first output circuits are configured to be deactivated responsive to a first feedback signal received by the intermediate stage via the feedback path.

2. The electronic circuit as recited in claim 1 , wherein the second input circuit and the second intermediate circuit are configured to cause the second output circuit to remain inactive responsive to the transition of the input signal from the first logic level to the second logic level.

3. The electronic circuit as recited in claim 1 , further comprising a keeper circuit coupled between the input node and the output node, wherein the keeper circuit is configured to drive the output signal at the second logic level on the output node subsequent to deactivation of the first output circuit.

4. The electronic circuit as recited in claim 3 , wherein, responsive to a transition of the input signal from the second logic level to the first logic level, the second input circuit is configured to:

activate the second intermediate circuit, and wherein, responsive thereto, the intermediate circuit is configured to activate the second output circuit, wherein when activated, and wherein, subsequent to a delay, the second intermediate and second output circuits are configured to be deactivated responsive to a second feedback signal received by the intermediate stage;

wherein when activated, the second output circuit drives the output signal on the output node, and wherein, subsequent to deactivation of the second output circuit, the keeper circuit is configured to provide the output signal at the first logic level on the output node.

5. The electronic circuit as recited in claim 3 , wherein the first input circuit and the first intermediate circuit are configured to cause the first output circuit to remain inactive responsive to the transition of the input signal from the second logic level to the first logic level.

6. The electronic circuit as recited in claim 4 , wherein the first intermediate circuit is configured to be deactivated responsive to receiving the second feedback signal.

7. The electronic circuit as recited in claim 4 , wherein the keeper circuit includes a plurality of inverters coupled in series, wherein the plurality of inverters includes an odd number of inverters.

8. The electronic circuit as recited in claim 3 , wherein the feedback path includes a first pair of devices configured to deactivate the first intermediate circuit and the first output stage responsive to receiving the feedback signal.

9. The electronic circuit as recited in claim 3 , wherein the feedback path includes a second pair of devices configured to deactivate the second intermediate circuit and the second output circuit responsive to receiving the feedback signal.

10. The electronic circuit as recited in claim 1 , wherein the second intermediate circuit is configured to be deactivated responsive to receiving the first feedback signal.

11. A method of operating an electronic circuit, the method comprising:

detecting a transition of an input signal from a first logic level to a second logic level;

activating a first input circuit responsive to said detecting;

activating a first intermediate circuit responsive to said activating the first input circuit;

activating first output circuit responsive to said activating the first intermediate circuit;

driving an output signal on an output node responsive to activating the first output circuit;

driving the output signal from the output node into a feedback path coupled between the output node and the first intermediate circuit receiving a first feedback signal at the first intermediate circuit via the feedback path;

deactivating the first intermediate circuit responsive to said receiving the feedback signal; and

deactivating the first output circuit responsive to said deactivating the first intermediate circuit.

12. The method as recited in claim 11 further comprising a second output circuit remaining inactive responsive to the transition of the input signal from the first logic level to the second logic level.

13. The method as recited in claim 12 further comprising, responsive to a transition of the input signal from the second logic level to the first logic level:

activating a second input circuit;

activating a second intermediate circuit responsive to activating the second input circuit;

activating the second output circuit responsive to activating the second intermediate circuit;

driving the output signal on the output node responsive to activating the second output circuit;

subsequent to a delay, deactivating the second intermediate circuit and the second output circuit responsive to a second feedback signal received by the second intermediate circuit; and

providing the output signal, at the first logic level, on the output node using a keeper circuit.

14. The method as recited in claim 13 further comprising the first input circuit and the first intermediate circuit inhibiting activation of the first output circuit responsive to the input signal transitioning from the second logic level to the first logic level.

15. The method as recited in claim 13 further comprising deactivating the first intermediate circuit responsive to receiving the second feedback signal.

16. The method as recited in claim 13 further comprising deactivating the second intermediate circuit responsive to receiving the first feedback signal.

17. The method as recited in claim 12 , further comprising the second input circuit inhibiting activation and the second intermediate circuit inhibiting activation of the second output circuit responsive to the input signal transitioning from the first logic level to the second logic level.

18. The method as recited in claim 11 , further comprising a keeper providing the output signal, at the second logic level, on the output node subsequent to deactivating the first output circuit.

19. An electronic circuit comprising:

a driver circuit configured to drive an output signal on an output node;

a first activation circuit configured to activate the driver circuit;

a second activation circuit configured to activate the first activation circuit responsive to detecting a transition of an input signal on an input node; and

a feedback path, wherein a first node of the feedback path is the output node and wherein a second node of the feedback path is coupled to the first activation circuit;

wherein the first activation circuit is configured to be deactivated responsive to receiving a feedback signal via the feedback path, wherein the feedback signal is generated responsive to activation of the driver circuit; and

wherein the driver circuit is configured to be deactivated responsive to deactivation of the first activation circuit.

20. The electronic circuit as recited in claim 19 , wherein the driver circuit is configured to drive the output signal on the output node at a first logic level responsive to the second activation circuit detecting an input signal transition from the first logic level to a second logic level; and

wherein the driver circuit is configured to drive the output signal on the output node at the second logic level responsive to the second activation circuit detecting an input signal transition from the second logic level to the first logic level.