Semiconductor storage device and method of manufacturing same
View Patent ↗Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and a select gate that intersects the word line. An insulating film is buried in the trench.
1. A semiconductor storage device comprising:
a plurality of first-conductivity-type diffusion regions extending in parallel with one another along one direction on a surface of a well of a second conductivity type;
a gate electrode extending along the one direction and being disposed on a substrate via a substrate insulating film between two mutually adjacent ones of said plurality of first-conductivity-type diffusion regions; and
a word line extending along a direction perpendicular to said one direction and three-dimensionally intersecting said gate electrode,
wherein an area of the well not covered by said gate electrode and said word line has a trench surrounding one of the plurality of first-conductivity-type diffusion regions within the area a trench insulating film being buried in said trench, and
wherein said trench is formed between said one of the plurality of first-conductivity-type diffusion regions and said gate electrode such that said one of the plurality of first conductivity-type diffusion regions and said gate electrode respectively contact opposing surfaces of sidewalls of said trench.
2. The device according to claim 1 , wherein said gate electrode and said substrate insulating film comprise a select gate,
wherein, at an intersection of said word line and said select gate, on a side wall of said select gate, a floating gate is provided, and said word line is provided on said select gate and said floating gate via a word line insulating film,
wherein a surface of said substrate has a common diffusion region of a first conductivity type disposed along a direction perpendicular to said one direction at a position spaced away from at least one longitudinal end of said plurality of first-conductivity-type diffusion regions, and
wherein said plurality of first-conductivity-type diffusion regions are connected to corresponding ones of bit lines arranged in a metal interconnect layer by contacts.
3. The device according to claim 2 , further comprising:
silicided contact regions on a surface of said plurality of said first-conductivity-type diffusion regions.
4. The device according to claim 3 , wherein a periphery of said plurality of said first-conductivity-type diffusion regions are covered by said trench insulating film, said trench insulating film comprising silicon dioxide,
wherein said trench insulating film fills said trench, and
wherein said silicided contact regions comprise metal silicide.
5. The device according to claim 4 , wherein said metal silicide comprises cobalt silicide.
6. The device according to claim 4 , further comprising:
a nitride film covering said select gate and said substrate insulating film.
7. The device according to claim 6 , wherein an interlayer dielectric film is formed on said nitride film, and
wherein said interlayer dielectric film comprises said metal interconnect layer.
8. The device according to claim 1 , wherein a bottom of said trench is formed below a bottom surface of said one of the plurality of first-conductivity-type diffusion regions.
9. The device according to claim 1 , wherein said trench is formed parallel to said one of the plurality of first-conductivity-type diffusion regions.
10. The device according to claim 1 , wherein said plurality of first-conductivity-type diffusion regions comprises a plurality of bit lines.
11. The device according to claim 1 , wherein said well of said second conductivity type comprises a memory cell area.
12. The device according to claim 1 , wherein said trench insulating film in said trench comprises a trench isolation.
13. The device according to claim 1 , wherein said plurality of first-conductivity-type diffusion regions are connected to corresponding ones of bit lines arranged in a metal interconnect layer via an upper-layer interconnection.
14. The device according to claim 1 , wherein said gate electrode is structurally separated from said word line.
15. The device according to claim 1 , wherein said gate electrode three-dimensionally intersects a plurality of word lines comprising said word line.
16. The device according to claim 1 , wherein said word line is unconnected to said gate electrode.
17. The device according to claim 1 , wherein said one of the plurality of first conductivity-type diffusion regions and said gate electrode respectively contact said opposing surfaces of sidewalls of said trench at a plane extending along said direction perpendicular to said one direction.
18. A semiconductor storage device, comprising:
a plurality of first-conductivity-type diffusion regions extending in parallel with one another along one direction on a surface of a well of a second conductivity type;
a gate electrode extending along the one direction and being disposed on a substrate via a substrate insulating film between two mutually adjacent ones of said plurality of first-conductivity-type diffusion regions; and
a word line extending along a direction perpendicular to said one direction and three-dimensionally intersecting said gate electrode,
wherein an area of the well not covered by said gate electrode and said word line has a trench surrounding one of the plurality of first-conductivity-type diffusion regions within the area, a trench insulating film being buried in said trench,
wherein said trench is formed between said one of the plurality of first-conductivity-type diffusion regions and said gate electrode such that said one of the plurality of first conductivity-type diffusion regions and said gate electrode contact a sidewall of said trench,
wherein said gate electrode and said substrate insulating film comprise a select gate,
wherein, at an intersection of said word line and said select gate, on a side wall of said select gate, a floating gate is provided, and said word line is provided on said select gate and said floating gate via a word line insulating film,
wherein a surface of said substrate has a common diffusion region of a first conductivity type disposed along a direction perpendicular to said one direction at a position spaced away from at least one longitudinal end of said plurality of first-conductivity-type diffusion regions,
wherein said plurality of first-conductivity-type diffusion regions arc connected to corresponding ones of bit tines arranged in a metal interconnect layer by contacts,
wherein said select gate intersects said common diffusion region via a common insulating film, and
wherein said select gate protrudes beyond a side edge of said common diffusion region.