IP Library Granted Patent US 8,016,941
Granted Patent B2
US 8,016,941 · App. 11/671,158 · Granted Sep 13, 2011

Method and apparatus for manufacturing a semiconductor

Assignees: Infineon Technologies AG; Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,016,941
App. No.
11/671,158
Granted
Sep 13, 2011
Kind
B2
Abstract

A method and apparatus for crystallizing a semiconductor that includes a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation, comprising amorphizing at least a portion of the second layer, applying a stress to the second layer and heating the second layer above a recrystallization temperature.

Claims (30)

1. A method for crystallizing a semiconductor, comprising:

providing a semiconductor substrate comprising a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation different from said first crystal lattice orientation;

subsequently amorphizing a portion of said second layer;

subsequently applying an external stress to said second layer; and

subsequently heating said second layer above a recrystallization temperature of said second layer to simultaneously cause said portion of said second layer to recrystallize with the first crystal lattice orientation of the first layer and bake stress from the external stress into said portion of said second layer.

2. The method of claim 1 , wherein applying said external stress comprises applying a stress liner over said second layer.

3. The method of claim 1 , wherein applying said external stress comprises bending said second layer.

4. The method of claim 1 , further comprising forming trenches in said substrate.

5. The method of claim 1 , further comprising removing said external stress after said heating.

6. The method of claim 5 , further comprising filling isolation trenches formed in said substrate after removing said external stress.

7. The method of claim 1 , wherein amorphizing said portion of said second layer comprises implanting ions in at least said portion of said second layer at a temperature above said recrystallization temperature of said second layer.

8. The method of claim 4 wherein applying said external stress comprises applying stress in said trenches.

9. A method of manufacturing semiconductor devices, comprising:

providing a semiconductor substrate comprising a first layer with a first crystal orientation and a second layer with a second crystal orientation different from said first orientation;

subsequently amorphizing a first region of said second layer;

subsequently applying an external stress to said second layer;

subsequently heating said second layer above a recrystallization temperature,

whereby said first region of said second layer is recrystallized with the first crystal lattice orientation of the first layer and simultaneously stress from the external stress is baked into said first region of said second layer; and

subsequently forming a first device in said first region of said second layer and a second device in a second region of said second layer.

10. The method of claim 9 , further comprising forming at least one isolation trench within said second layer.

11. The method of claim 9 , wherein said first device is a p-channel transistor and said second device is an n-channel transistor.

12. The method of claim 10 , wherein applying said external stress comprises applying said stress in said at least one isolation trench.

13. A method of fabricating semiconductor circuits, comprising:

providing a semiconductor substrate;

subsequently amorphizing a portion of said substrate;

subsequently applying stress to said substrate;

subsequently heating said substrate above a recrystallization temperature of said substrate to simultaneously cause said portion of said second layer to recrystallize and cause the external stress to become baked into said portion of said second layer; and

subsequently fabricating electronic devices in said substrate.

14. The method of claim 13 , wherein said substrate comprises a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation different from said first crystal lattice orientation, and wherein amorphizing said portion of said substrate and fabricating said electronic devices in said substrate are performed in said second layer.

15. The method of claim 13 , further comprising removing said stress after heating said substrate above said recrystallization temperature.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2007
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 019267/0186 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2007
From: HIERLEMANN, MATTHIAS
To: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Reel/Frame 018852/0713 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2007
From: KU, JA-HUM
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 018852/0819 →
Continuity (1)
Related Publication 20080188046A1 · Aug 7, 2008