Method and system for reconfigurable pattern filtering engine
Methods and systems for a reconfigurable pattern filtering engine may include assembling a hardware filter from a plurality of minimum length hardware filters. A length of the assembled hardware filter may vary in multiples of a length of one of the minimum length hardware filters. The assembled hardware filter and the minimum length hardware filters may be integrated within a single chip. Specific messages in the data stream may be filtered using the assembled hardware filter. The assembled hardware filter may use at least one filter coefficient, an inclusion mask, and an exclusion mask to filter messages. At least a portion of the filtered messages may be stored in memory via direct memory access transfers.
1. A method for communication, the method comprising:
determining a set of hardware filters to use for identifying one or more particular packets in a data stream;
assembling each hardware filter of said set from a plurality of minimum length hardware filters, wherein:
a length of said each assembled hardware filter is a multiple of a length of one or more of said minimum length hardware filters; and
said assembling of said each assembled hardware filter comprises concatenating two or more of said plurality of minimum length hardware filters until a combined length of said concatenated two or more of said plurality of minimum length hardware filters is equal to said length of said each assembled hardware filter; and
filtering said one or more particular packets in said data stream using said determined set of hardware filters.
2. The method according to claim 1 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are contiguously arranged.
3. The method according to claim 1 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are non-contiguously arranged.
4. The method according to claim 1 , comprising configuring said each assembled hardware filter using at least one filter coefficient.
5. The method according to claim 4 , wherein said at least one filter coefficient is stored in a table in memory.
6. The method according to claim 1 , comprising configuring said each assembled hardware filter using at least one filter mask.
7. The method according to claim 6 , wherein said filter mask is at least one of the following: an inclusion mask and an exclusion mask.
8. The method according to claim 1 , comprising storing at least a portion of said filtered specific message to memory.
9. The method according to claim 8 , wherein said storing occurs via direct memory access transfers.
10. The method according to claim 1 , wherein said each assembled hardware filter and at least one of said minimum length hardware filters used in assembling said each assembled hardware filter are integrated within a single chip.
11. A non-transitory machine-readable storage medium having stored thereon, a computer program having at least one code section for communication, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
determining a set of hardware filters to use for identifying one or more particular packets in a data stream;
assembling each hardware filter of said set from a plurality of minimum length hardware filters, wherein:
a length of said each assembled hardware filter is a multiple of a length of one or more of said minimum length hardware filters; and
said assembling of said each assembled hardware filter comprises concatenating two or more of said plurality of minimum length hardware filters until a combined length of said concatenated two or more of said plurality of minimum length hardware filters is equal to said length of said each assembled hardware filter; and
filtering said one or more particular packets in said data stream using said determined set of hardware filters.
12. The machine-readable storage according to claim 11 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are contiguously arranged.
13. The machine-readable storage according to claim 11 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are non-contiguously arranged.
14. The machine-readable storage according to claim 11 , wherein said at least one code section comprises code for configuring said each assembled hardware filter using at least one filter coefficient.
15. The machine-readable storage according to claim 14 , wherein said at least one filter coefficient is stored in a table in memory.
16. The machine-readable storage according to claim 11 , wherein said at least one code section comprises code for configuring said each assembled hardware filter using at least one filter mask.
17. The machine-readable storage according to claim 16 , wherein said filter mask is at least one of the following: an inclusion mask and an exclusion mask.
18. The machine-readable storage according to claim 11 , wherein said at least one code section comprises code for storing at least a portion of said filtered specific message to memory.
19. The machine-readable storage according to claim 18 , wherein said storing occurs via direct memory access transfers.
20. The machine-readable storage according to claim 11 , wherein said each assembled hardware filter and said at least one of said minimum length hardware filters used in assembling said each assembled hardware filter are integrated within a single chip.
21. A system for processing information in a data stream, the system comprising:
circuitry that enables determination of a set of hardware filters to use for identifying one or more particular packets in a data stream;
circuitry that enables assembling of each hardware filter of said set from a bank of minimum length hardware filters, wherein:
a length of said each assembled hardware filter is a multiple of a length of one or more of said minimum length hardware filters; and
said assembling of said each assembled hardware filter comprises concatenating two or more of said bank of said minimum length hardware filters until a combined length of said concatenated two or more of said bank of said minimum length hardware filters is equal to said length of said each assembled hardware filter; and
circuitry that enables filtering of said one or more particular packets in said data stream using said determined set of hardware filters.
22. The system according to claim 21 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are contiguously arranged.
23. The system according to claim 21 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are non-contiguously arranged.
24. The system according to claim 21 , comprising circuitry that enables configuring of said each assembled hardware filter using at least one filter coefficient.
25. The system according to claim 24 , wherein said at least one filter coefficient is stored in a table in memory.
26. The system according to claim 21 , comprising circuitry that enables configuring of said each assembled hardware filter using at least one filter mask.
27. The system according to claim 26 , wherein said filter mask is at least one of the following: an inclusion mask and an exclusion mask.
28. The system according to claim 21 , comprising circuitry that enables storing of at least a portion of said filtered specific message to memory.
29. The system according to claim 28 , wherein said storing occurs via direct memory access transfers.
30. The system according to claim 21 , wherein said each assembled hardware filter and said at least one of said minimum length hardware filters used in assembling said each assembled hardware filter are integrated within a single chip.
31. A method for communication, the method comprising:
assembling a set of hardware filters to use for identifying one or more particular packets in a data stream, wherein:
each hardware filter, in said set of hardware filters, is assembled from a plurality of minimum length hardware filters, wherein:
a length of said each hardware filter is a multiple of a length of one or more of said minimum length hardware filters; and
said assembling of said each hardware filter comprises concatenating two or more of said plurality of minimum length hardware filters until a combined length of said concatenated two or more of said plurality of minimum length hardware filters is equal to said length of said each hardware filter; and
filtering said one or more particular packets in said data stream using said determined set of hardware filters.
32. The method according to claim 31 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are contiguously arranged.
33. The method according to claim 31 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are non-contiguously arranged.
34. The method according to claim 31 , comprising configuring said each assembled hardware filter using at least one filter coefficient.
35. The method according to claim 34 , wherein said at least one filter coefficient is stored in a table in memory.
36. The method according to claim 31 , comprising configuring said each assembled hardware filter using at least one filter mask.
37. The method according to claim 36 , wherein said filter mask is at least one of the following: an inclusion mask and an exclusion mask.
38. The method according to claim 31 , comprising storing at least a portion of said filtered specific message to memory.
39. The method according to claim 38 , wherein said storing occurs via direct memory access transfers.
40. The method according to claim 31 , wherein said each assembled hardware filter and at least one of said minimum length hardware filters used in assembling said each assembled hardware filter are integrated within a single chip.
41. A system for communication, the system comprising:
one or more circuits comprising a plurality of minimum length hardware filters, said one or more circuits being operable to assemble a set of hardware filters to use for identifying one or more particular packets in a data stream, wherein:
each hardware filter, in said set of hardware filters, is assembled from said plurality of minimum length hardware filters, wherein:
a length of said each hardware filter is a multiple of a length of one or more of said minimum length hardware filters; and
said assembling of said each hardware filter comprises concatenating two or more of said plurality of minimum length hardware filters until a combined length of said concatenated two or more of said plurality of minimum length hardware filters is equal to said length of said each hardware filter; and
said one or more circuits are operable to filter said one or more particular packets in said data stream using said determined set of hardware filters.
42. The system according to claim 41 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are contiguously arranged.
43. The system according to claim 41 , wherein at least a portion of said each assembled hardware filter comprises a plurality of said minimum length hardware filters that are non-contiguously arranged.
44. The system according to claim 41 , wherein said one or more circuits are operable to configure said each assembled hardware filter using at least one filter coefficient.
45. The system according to claim 44 , wherein said at least one filter coefficient is stored in a table in memory.
46. The system according to claim 41 , wherein said one or more circuits are operable to configure said each assembled hardware filter using at least one filter mask.
47. The system according to claim 46 , wherein said filter mask is at least one of the following: an inclusion mask and an exclusion mask.
48. The system according to claim 41 , wherein said one or more circuits are operable to store at least a portion of said filtered specific message to memory.
49. The system according to claim 48 , wherein said storing occurs via direct memory access transfers.
50. The system according to claim 41 , wherein said each assembled hardware filter and at least one of said minimum length hardware filters used in assembling said each assembled hardware filter are integrated within a single chip.