Semiconductor device and method of manufacturing the same
View Patent ↗A metal interconnection of semiconductor device and method for fabricating the same is provided. The semiconductor device can include a semiconductor substrate formed with device structures such as transistors. An interlayer dielectric layer can be formed on the semiconductor substrate with a metal interconnection formed therethrough. A spacer can be formed on at least a portion of a sidewall of the metal interconnection. A diffusion barrier can be formed on an upper surface of the metal interconnection.
1. A method of manufacturing a semiconductor device, comprising:
forming an interlayer dielectric layer on a semiconductor substrate;
forming a metal interconnection through the interlayer dielectric layer;
forming a spacer comprising Ta or TaN at a portion of a sidewall of the metal interconnection; and
forming a diffusion barrier on an upper surface of the metal interconnection by depositing a diffusion barrier material on the metal interconnection having the spacer after forming the spacer at the portion of the sidewall of the metal interconnection.
2. The method according to claim 1 , wherein forming the metal interconnection comprises:
forming a via trench hole in the interlayer dielectric layer by performing a damascene process;
forming a barrier metal layer and a seed layer in the via trench hole; and
forming a copper layer on the seed layer.
3. The method according to claim 1 , wherein forming the diffusion barrier comprises performing an electroless plating process.
4. The method according to claim 3 , wherein the diffusion barrier comprises cobalt and tungsten.
5. The method according to claim 1 , wherein forming the spacer comprises:
recessing the interlayer dielectric layer such that at least the portion of the sidewall of the metal interconnection is exposed;
depositing a metal layer comprising the Ta or TaN on the interlayer dielectric layer including the metal interconnection; and
etching the metal layer such that the spacer is formed at the sidewall of the metal interconnection.
6. The method according to claim 5 , wherein recessing the interlayer dielectric layer comprises performing a wet-etch.
7. The method according to claim 6 , wherein performing the wet-etch comprises using a BOE (buffered oxide etchant) solution.
8. The method according to claim 7 , wherein the BOE solution comprises fluorine.
9. The method according to claim 5 , wherein etching the metal layer comprises using etching gas including a halogen element.
10. The method according to claim 9 , wherein the halogen element is Cl, Br or F.