IP Library Granted Patent US 8,026,574
Granted Patent B2
US 8,026,574 · App. 12/814,124 · Granted Sep 27, 2011

Anti-fuse memory cell

Assignee: Sidense Corporation
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Quick Facts
Patent No.
US 8,026,574
App. No.
12/814,124
Granted
Sep 27, 2011
Kind
B2
Abstract

An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.

Claims (9)

1. A non-volatile memory cell formed on a substrate with a CMOS fabrication process capable of forming structures with a predefined minimum feature size i, where i is a numerical value in nm, comprising:

a polysilicon gate over a channel region having a channel length and a channel width;

a diffusion region proximate to a first end of the channel region;

a field oxide region proximate to a second end of the channel region;

a variable thickness gate oxide between the polysilicon gate and the substrate, the variable thickness gate oxide having a thick gate oxide portion and a thin gate oxide portion fusible to form a conductive link between the polysilicon gate and the substrate, the thin gate oxide portion being formed over the channel region and having dimensions less than the minimum feature size i.

2. The non-volatile memory cell of claim 1 , wherein the thin gate oxide portion is rectangular in shape.

3. The non-volatile memory cell of claim 2 , wherein a first side and a second side of the rectangle are bound by the thick gate oxide portion and a third side and a fourth side of the rectangle are bound by the channel region.

4. The non-volatile memory cell of claim 1 , wherein the thin gate oxide portion is triangular in shape.

5. The non-volatile memory cell of claim 4 , wherein a first side and a second side of the triangle are bound by the channel region and a diagonal side of the triangle is bound by the thick gate oxide portion.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2017
From: SIDENSE CORP.
To: SYNOPSYS, INC.
Reel/Frame 044958/0571 →
SECURITY INTEREST Recorded May 21, 2014
From: SIDENSE CORP.
To: COMERICA BANK
Reel/Frame 032981/0930 →
Continuity (4)
Continuation 11762552 · Jun 13, 2007
Continuation In Part 10553873
Provisional Application 60568315 · May 6, 2004
Related Publication 20100244115A1 · Sep 30, 2010