Lazy handling of end of interrupt messages in a virtualized environment

1. One or more computer-readable media storing computer-executable instructions that, when executed on one or more processors, perform acts comprising:

receiving an interrupt service request from a hypervisor;

sending the interrupt service request to a central processing unit (CPU);

receiving an End Of Interrupt (EOI) acknowledgment from the CPU;

determining whether a processing criteria is met;

writing a value to a memory shared with the hypervisor if the criteria is met; and

sending the EOI to the hypervisor if the criteria is not met.

2. One or more computer-readable media as recited in claim 1 , wherein the value written to memory comprises a bit.

3. One or more computer-readable media as recited in claim 1 , wherein sending the EOI to the hypervisor comprises writing to a memory mapped page, wherein a memory intercept module running within the hypervisor traps the writing to the memory mapped page.

4. One or more computer-readable media as recited in claim 1 , wherein the memory shared with the hypervisor comprises a page of physical memory simultaneously mapped to a page of guest operating system virtual memory and a page of hypervisor virtual memory.

5. One or more computer-readable media as recited in claim 1 , wherein writing the value to the memory enables delaying processing the EOI until the hypervisor begins execution for a reason other than processing the EOI.

6. One or more computer-readable media as recited in claim 1 , wherein the act of determining whether a processing criteria is met further includes:

reading a value indicating whether the EOI may be lazily processed from a shared memory.

7. One or more computer-readable media as recited in claim 6 , wherein the shared memory is shared with the hypervisor, and wherein the hypervisor indicates in the shared memory that an EOI cannot be lazily evaluated when the received interrupt comprises a level-triggered interrupt.

8. One or more computer-readable media as recited in claim 6 , wherein the shared memory is shared with the hypervisor, and wherein the hypervisor indicates in the shared memory that an EOI cannot be lazily evaluated when:

a second interrupt received after receiving a first interrupt comprises a priority lesser than a priority of the first interrupt; and

the CPU is processing the first interrupt.

9. One or more computer-readable media as recited in claim 6 , wherein the shared memory is shared with the hypervisor, and wherein the hypervisor indicates in the shared memory that an EOI cannot be lazily evaluated when:

a second interrupt received after receiving a first interrupt comprises a priority greater than a priority of the first interrupt; and

the CPU is processing the first interrupt.

10. A method comprising:

receiving an interrupt;

analyzing a virtual Advanced Programmable Interrupt Controller (APIC) associated with a virtual CPU to determine whether a criteria is met;

setting a value of a memory shared with a guest operating system to indicate that the guest operating system can lazily process an End Of Interrupt (EOI) when the guest operating system can lazily process an EOI acknowledgment; and

otherwise setting the value of the memory shared with the guest operating system to indicate that the guest operating system cannot lazily process an EOI.

11. A method as described in claim 10 , wherein the guest operating system can lazily process the EOI when the interrupt comprises an edge-triggered interrupt.

12. A method as described in claim 10 , wherein the interrupt comprises a first interrupt, and wherein the guest operating system is configured not to lazily process an EOI acknowledgment when:

a second interrupt received after receiving the first interrupt comprises a priority lesser than a priority of the first interrupt; and

the virtual CPU is processing the first interrupt.

13. A method as described in claim 10 , wherein the interrupt comprises a first interrupt, and wherein the guest operating system is configured not to lazily process an EOI acknowledgment when:

a second interrupt received after receiving the first interrupt comprises a priority greater than a priority of the first interrupt; and

the virtual CPU is processing the second interrupt.

14. A method as described in claim 10 , wherein the guest operating system can lazily process an EOI acknowledgment when the interrupt comprises an edge-triggered interrupt and when the interrupt is the only interrupt being processed.

15. A method as described in claim 10 further comprising:

receiving an EOI directly from the guest operating system.

16. A method as described in claim 10 further comprising:

retrieving a value stored in the memory shared with the guest operating system indicating whether an EOI occurred, the value retrieved other than in response to the EOI.

17. A method as described in claim 10 , wherein a memory intercept module is installed on a page of memory, the page of memory comprising a memory-mapped I/O page used by the virtual CPU to communicate with a physical APIC.

18. A computer system comprising:

one or more processors;

memory, accessible by the one or more processors;

a hypervisor stored in memory and executable on the one or more processors to:

receive an interrupt,

determine whether a first processing criteria is met,

set a value in a shared memory indicating that an End Of Interrupt (EOI) can be lazily evaluated when the first processing criteria is met,

set a value in a shared memory indicating that the EOI must be transferred to the hypervisor upon completion of handling the interrupt if the first processing criteria is not met, and

transmit the interrupt to a virtual CPU executing a guest operating system; and

a lazy End Of Interrupt (EOI) processing module of the guest operating system stored in memory and executable on the one or more processors to:

receive an EOI from the virtual CPU indicating the interrupt has been executed,

determine whether a second processing criteria is met;

send the EOI to the hypervisor if the second processing criteria is met,

set a value in the shared memory indicating that the EOI occurred, enabling the hypervisor to respond to the EOI at a later time if the second processing criteria is not met.

19. The computer system as recited in claim 18 , wherein an End Of Interrupt (EOI) acknowledgment to the interrupt can be lazily evaluated when:

the interrupt is not a level-triggered interrupt, and

the interrupt is the only active interrupt.

20. The computer system as recited in claim 18 , wherein the interrupt is a self-interrupt, and the hypervisor communicates the self-interrupt to a virtual local APIC associated with the virtual CPU.