Methods of fabricating semiconductor device having capacitorless one-transistor memory cell
A method of fabricating a semiconductor device having a capacitorless one-transistor memory cell includes forming a first floating body pattern on a lower insulating layer of a substrate and a first gate pattern crossing over the first floating body pattern and covering sidewalls of the first floating body pattern is formed. The first floating body pattern at both sides of the first gate pattern is partially etched to form a protrusion portion extending between and above the partially etched regions, and first impurity regions are formed in the partially etched regions of the first floating body pattern.
1. A method of fabricating a semiconductor device, comprising:
forming a first floating body pattern on a lower insulating layer of a substrate;
forming a first gate pattern on the first floating body pattern, the first gate pattern crossing over the first floating body pattern and covering sidewalls of the first floating body pattern;
partially etching the first floating body pattern at both sides of the first gate pattern to form etched regions at both sides of the first gate pattern, such that the first floating body pattern has a protrusion portion between the etched regions, and the protrusion extends above the etched regions; and
forming first impurity regions in the etched regions of the first floating body pattern.
2. The method as claimed in claim 1 , further comprising:
forming a second floating body pattern spaced apart from the first floating body pattern on the insulating layer, forming of the first and second floating body patterns being simultaneous; and
forming a second gate pattern crossing over the second floating body pattern, forming of the first and second gate patterns being simultaneous.
3. The method as claimed in claim 2 , further comprising forming an isolation pattern surrounding sidewalls of the second floating body pattern.
4. The method as claimed in claim 3 , wherein forming the isolation pattern comprises:
forming an isolation layer on the substrate having the first and second floating body patterns, wherein the isolation layer includes an insulating liner and an isolation insulating layer on the insulating liner, the insulating liner being formed of a material layer having an etch selectivity with respect to the bottom insulating layer and the isolation insulating layer; and
sequentially etching the isolation insulating layer and the insulating liner adjacent to the first floating body pattern to expose a top surface and a sidewall of the first floating body pattern.
5. The method as claimed in claim 1 , further comprising forming gate spacers covering sidewalls of the first gate pattern and extending over sidewalls of the protrusion portion of the first floating body pattern before forming the first impurity regions.
6. The method as claimed in claim 1 , further comprising forming first gate spacers covering sidewalls of the first gate pattern before forming the etched regions, wherein the first gate spacers and the first gate pattern are used as etch masks to partially etch the first floating body pattern.
7. The method as claimed in claim 6 , further comprising forming second gate spacers covering the first gate spacers and extending over sidewalls of the protrusion portion of the first floating body pattern before forming the first impurity regions.
8. The method as claimed in claim 1 , wherein the protrusion portion of the first floating body pattern is formed to have a greater width than a width of the gate pattern.
9. The method as claimed in claim 1 , wherein the protrusion portion of the first floating body pattern is formed to have a smaller width than a distance between facing sidewalls of adjacent first impurity regions.
10. The method as claimed in claim 1 , wherein the protrusion portion is formed not to overlap the first impurity regions.
11. The method as claimed in claim 1 , wherein forming the first impurity regions includes defining at least a part of the first floating body pattern between the first impurity regions and at a lower part of the first gate pattern as a charge storage region of a DRAM cell.
12. The method as claimed in claim 1 , wherein forming the first floating body pattern includes forming at least two regions of different characteristics, such that an upper region of the at least two regions is disposed in the protrusion portion of the first floating body pattern.
13. The method as claimed in claim 12 , wherein partially etching the first floating body pattern includes removing the upper region of the at least two regions from both sides of the first gate pattern to form the recessed regions.
14. The method as claimed in claim 12 , wherein the recessed regions are formed to have different characteristics than the protrusion portion.