Simplified pixel cell capable of modulating a full range of brightness
A simplified pixel display includes a plurality of pixel electrodes, a plurality of storage elements, a single arbitrary voltage supply terminal, a second voltage supply terminal which may be either of the rail voltages of the display, a common electrode, and a plurality of externally controlled switches each selectively coupling an associated one of the pixel electrodes with one of the arbitrary voltage supply terminal and the second voltage supply terminal responsive to a value of a data bit stored in an associated one of said storage elements and to the state of the external control signal supplied to the switch.
1. A pulse width modulated display system comprising:
a display controller to deliver voltages, control logic signals and image data to the display system; and
an array of pixels, of which each pixel comprises the following elements:
a SRAM memory cell having two complementary outputs;
a DC balance control circuit controlled by a plurality of external control signals;
a two-transistor inverter to apply one of two voltages to a pixel mirror;
a single voltage source independent of voltage rails of the pixel array of the display system; and
a counter electrode disposed opposite the array of pixels and operated at a voltage potential independent of the voltage potential of the pixels,
wherein the complementary outputs of said SRAM memory cell are both presented to the DC balance control circuit;
wherein the DC balance control circuit, responsive to the configuration of the external control signals asserts one of the two complementary outputs of the SRAM memory cell to gates of the two transistors of the inverter; and
wherein the inverter, responsive to the voltage asserted on the gates of its transistors, applies one of two voltages to the pixel mirror for that pixel.
2. The display system of claim 1 wherein the memory cell is a six-transistor SRAM cell.
3. The display system of claim 1 wherein the rail voltage available to the inverter to be applied to the pixel mirror is the upper rail voltage (V DD ).
4. The display system of claim 3 wherein the independent voltage V X lies between the upper and lower rail voltages (V DD and V SS ) of the array of pixels.
5. The display system of claim 1 wherein the rail voltage available to the inverter to be applied to the pixel mirror is the lower rail voltage (V SS ).
6. The display system of claim 5 wherein the independent voltage V X lies between the upper and lower rail voltages (V DD and V SS ).
7. The display system of claim 1 wherein the DC balance control circuit is compatible with operation of the liquid crystal cell over the full extent of the range between the upper and lower rail voltages.
8. The display system of claim 1 wherein the DC balance control circuit is compatible with operation over a portion of the voltage range between the upper rail and the lower rail, being limited by proximity to the voltage of the lower rail.
9. The display system of claim 1 wherein the inverter comprises one p-channel transistor and one n-channel transistor.
10. The display system of claim 7 wherein the DC balance control circuit comprises two pairs of transistors, each pair comprising one p-channel transistor and one n-channel transistor, wherein the gates of each pair are operated by a separate control line according to a “break before make” logic as an XOR gate.
11. The display system of claim 8 wherein the DC balance control circuit comprises two p-channel transistors operating as an XOR gate.
12. The display system of claim 1 wherein the display controller applies one of two voltages to the counter electrode in time synchronization with the operation of the DC balance circuit.
13. The display system of claim 12 wherein the two voltages to be applied to the counter electrode are selected such that the magnitude of the difference between a first voltage to be applied to the counter electrode and a first voltage to be applied to a pixel electrode is substantially equal to the magnitude of the difference between a second voltage to be applied to the counter electrode and a second voltage to be applied to a pixel electrode.
14. The display system of claim 12 wherein the duration of a first DC balance state is substantially equal to the duration of a second DC balance state.
15. The display system of claim 1 wherein different parts of the display circuits have different V DD voltages.
16. The display system of claim 15 wherein V DD of the pixel array differs from V DD of other parts of the display system.
17. The display system of claim 1 wherein V DD of the inverter is provided by a line separate from the V DD supply line of the other components pixel array.
18. The display system of claim 1 wherein V DD of the inverter is provided by a line common to the V DD line of the other components of the pixel circuit.