Bit set modes for a resistive sense memory cell array
View Patent ↗Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
1. A method comprising:
identifying a group of resistive sense memory (RSM) cells in a non-volatile semiconductor memory array to be subjected to a bit set operation;
selecting a bit set value from a plurality of bit set values each separately writable to said cells to place said cells in a selected resistive state;
performing a write-read verify operation by writing the selected bit set value to each of the RSM cells in said group, followed by reading each of the RSM cells in said group to ensure the selected bit set value remains stored in said RSM cells; and
writing user data from a host device to said RSM cells in relation to the selected bit set value so that less than all of said RSM cells are switched to a different selected bit set value.
2. The method of claim 1 , wherein the selected bit set value comprises a logical 0 and the different selected bit set value comprises a logical 1.
3. The method of claim 1 , wherein the selected bit set value is a multi-bit value.
4. The method of claim 1 , wherein the identifying, selecting and performing steps are carried out during a first pass through the method using a first selected bit set value that places each of the RSM cells in said group in a lowest resistance state prior to the writing step, and wherein the identifying, selecting and performing steps are carried out during a second pass through the method using a second selected bit set value that places each of the RSM cells in said group in a highest resistance state prior to the writing step.
5. The method of claim 1 , wherein the performing step comprises flowing a write current through each of the RSM cells in turn to set each of the RSM cells to a common resistive state.
6. The method of claim 1 , further comprising identifying protected data stored in the RSM cells in said group, reading and temporarily storing the protected data prior to the performing step, and transferring the protected data back to the array after the performing step so that at least a selected one of the RSM cells verified during the performing step as storing the selected bit set value is written to a different bit set value.
7. The method of claim 1 , wherein the RSM cells are characterized as spin-torque transfer random access memory (STRAM) cells.
8. The method of claim 1 , wherein the RSM cells are characterized as resistive random access memory (RRAM) cells.
9. An apparatus comprising:
a non-volatile semiconductor memory array of resistive sense memory (RSM) cells; and
a controller configured to execute a bit set operation by identifying a group of said RSM cells, selecting a bit set value from a plurality of bit set values each separately writable to said cells to place said cells in a selected resistive state, writing the selected bit set value to the RSM cells in said group, and reading said RSM cells to ensure the selected bit set value remains stored in said RSM cells prior to a conclusion of the bit set operation, the controller further configured to subsequently execute a write operation by overwriting user data from a host device to the RSM cells in said group in relation to the selected bit set value.
10. The apparatus of claim 9 , wherein the write operation changes a first portion of the RSM cells in said group to a different selected bit set value and leaves a second portion of the RSM cells in said group with the selected bit value.
11. The apparatus of claim 9 , in which the group of resistive sense memory (RSM) cells in the array to be subjected to the bit set operation constitutes less than all of the RSM cells in said array.
12. The apparatus of claim 9 , wherein the controller executes a first bit set operation to place a first set of the RSM cells in a lowest resistance state, directs a writing of first user data from the host device to at least one of the first set of the RSM cells to overwrite said lowest resistance state, executes a second bit set operation to place a second set of the RSM cells in a highest resistance state, and directs a writing of second user data from the host device to at least one of the second set of the RSM cells to overwrite said highest resistance state.
13. The apparatus of claim 9 , wherein the controller writes the selected bit value by directing a write current to flow through each of the RSM cells in turn to set each of the RSM cells to a common resistive state.
14. The apparatus of claim 9 , wherein the selected bit set value is characterized as a first bit set value which places an associated RSM cell in a low resistance state, wherein the controller further selects a different second bit set value from said plurality of bit set values which places an associated RSM cell in a high resistance state, and wherein the controller concurrently writes the second bit set value to a remaining portion of said RSM cells of said group while writing the first bit set value to said portion of the RSM cells in said group followed by a read-verify operation upon said remaining portion of said RSM cells.
15. The apparatus of claim 9 , in which the bit set operation further operates to read and temporarily store protected data stored in the portion of the RSM cells in a separate memory location prior to the writing and reading steps, and operates to transfer the protected data from the separate memory back to said portion of the RSM cells after the writing and reading steps.
16. A method comprising:
identifying a group of resistive sense memory (RSM) cells in a non-volatile semiconductor memory array to be subjected to a bit set operation;
selecting a bit set value from a plurality of bit set values each separately writable to said cells to place said cells in a selected resistive state;
reading protected data from at least selected RSM cells in said group and temporarily storing the protected data in a separate memory location;
writing the selected bit set value to each of the RSM cells in the group;
transferring the protected data from the separate memory location back to the array so that the at least selected RSM cells in said group are overwritten with a different, second bit set value; and
overwriting input user data from a host device to the RSM cells in the group in relation to the selected bit set value after the transferring step to achieve write power consumption efficiencies.
17. The method of claim 16 , in which the writing step is characterized as a write-read verify operation that further comprises reading the selected bit set value from each of the RSM cells to ensure the selected bit set value was correctly written to each said cell.
18. The method of claim 17 , in which the group of resistive sense memory (RSM) cells in the array to be subjected to the bit set operation constitutes less than all of the RSM cells in said array.
19. The method of claim 16 , in which the plurality of bit set values of the selecting step comprise a logical 0 value and a logical 1 value, and the selected bit value comprises the logical 0 value.
20. The method of claim 16 , further comprising performing a read-verify operation prior to the overwriting step to ensure the selected bit value was successfully written to the RSM cells in the group during the writing step.