Method and apparatus for verifying integrated circuit design using a constrained random test bench

1. A constrained random test bench for verifying an integrated circuit design, comprising:

an instruction streamer configured to:

hold an instruction sequence for verifying a particular mode of operation of an integrated circuit design, wherein the instruction sequence has a corresponding first priority; and

detect an interrupt condition and queue an interrupt service routine instruction sequence a random time after detecting the interrupt condition, wherein the interrupt service routine instruction sequence has a corresponding second priority;

a priority scheduler in communication with the instruction streamer, the priority scheduler operable to:

issue the instruction sequence when the first priority is higher than the second priority; and

issue the interrupt service routine instruction sequence when the second priority is higher than the first priority;

wherein the instruction sequence and the interrupt service routine instruction sequence are each issued one instruction at a time; and

an instruction translator in communication with the priority scheduler, the instruction translator configured to receive the issued instruction and apply it to the integrated circuit design to perform a requested operation, wherein an expected data value associated with the requested operation is stored in a particular register of a mirror memory; and

wherein the instruction streamer is further configured to hold a second instruction sequence to:

read a register of the integrated circuit design to retrieve a register data value, wherein the register of the integrated circuit design corresponds to the particular register of the mirror memory;

compare expected data value to the register data value;

provide an indication that the requested operation is a success when the expected data value matches the register data value; and

provide an indication that the requested operation is a failure when the expected data value does not match the register data value.

2. The constrained random test bench of claim 1 , further comprising a test manager in communication with the instruction streamer, the test manager operable to start and stop the instruction streamer.

3. The constrained random test bench of claim 1 , wherein the instruction streamer is a noise instruction streamer operable to randomly issue an instruction that lies outside the address space of a chip design.

4. The constrained random test bench of claim 1 , wherein the instruction streamer is a customized instruction streamer operable to issue a valid randomized instruction sequence at a specified time during a simulation.

5. The constrained random test bench of claim 1 , wherein the instruction streamer is a program instruction streamer operable to issue a valid randomized instruction sequence based, at least in part, on a constraint.

6. The constrained random test bench of claim 5 , wherein the constraint specifies an order of an order dependent instruction.

7. The constrained random test bench of claim 1 , wherein the priority scheduler is further configured to select an instruction from the instruction streamer based on a priority and issue the instruction to the instruction translator.

8. The constrained random test bench of claim 1 , wherein the instruction translator is further configured to translate the instruction into a sequence of one or more low level hardware commands.

9. The constrained random test bench of claim 1 , wherein the instruction streamer comprises a plurality of instruction streamers, each having a particular priority level and wherein the priority scheduler selects an instruction from an instruction streamer based on a priority level.

10. A method for performing a constrained random test during a verification of a chip design, comprising:

receiving an indication of a test to apply to a chip design, the test being executed at a test bench, and the test bench comprising a processor to execute one or more executable components;

storing an expected data value associated with the test in a particular register of a mirror memory;

constructing a plurality of instruction sequences to implement the test at a test case generator executing on the test bench;

executing a first instruction from a first instruction sequence of the plurality of instruction sequences at an instruction translator executing on the test bench, the first instruction having a first priority;

detecting an interrupt condition and queuing a second instruction sequence of the plurality of instruction sequences a random time after detecting the interrupt condition at an instruction streamer executing on the test bench, the second instruction sequence comprising an interrupt service routine instruction sequence and having a second priority;

determining that the second priority of the second instruction sequence is higher than the first priority of the first instruction sequence at a priority scheduler executing on the test bench;

executing the interrupt service routine instruction sequence after the first instruction completes at the instruction translator executing on the test bench;

reading a register of the chip design to retrieve a register data value, wherein the register of the integrated circuit design corresponds to the particular register of the mirror memory;

comparing the expected data value to the register data value;

providing an indication that the requested operation is a success when the expected data value matches the register data value; and

providing an indication that the requested operation is a failure when the expected data value does not match the register data value.

11. The method of claim 10 wherein the first instruction sequence is a randomized instruction sequence.

12. The method of claim 10 , further comprising executing a third instruction sequence of instructions that lie outside the address space of a chip design under test when there are no higher priority instruction sequences awaiting execution.

13. The method of claim 10 , wherein the indication further comprises a valid sequence of one or more instructions and a constraint condition.

14. A method for performing a constrained random test during a verification of a chip design, comprising:

receiving an indication of a test to be executed at a test bench, the test bench comprising a processor to execute one or more executable components;

storing an expected data value associated with the test in a particular register of a mirror memory;

constructing a plurality of instruction sequences, each instruction sequence including one or more instructions at a test case generator executing on the test bench, wherein each of the one or more instructions is an atomic instruction;

issuing each instruction sequence to a corresponding one of a plurality of instruction queues at a priority scheduler executing on the test bench;

executing a first atomic instruction from a first instruction queue of the plurality of instruction queues at an instruction translator executing on the test bench;

translating the first atomic instruction into a low level hardware command at the instruction translator;

determining that a second instruction queue of the plurality of instruction queues having a higher priority than the first instruction queue has a second instruction sequence awaiting execution at a priority scheduler executing on the test bench;

executing one or more second atomic instructions included in the second instruction sequence after the first atomic instruction completes at the instruction translator executing on the test bench;

translating the one or more second atomic instructions into one or more second low level hardware commands at the instruction translator;

reading a register of the chip design to retrieve a register data value, wherein the register of the integrated circuit design corresponds to the particular register of the mirror memory;

comparing the expected data value to the register data value;

providing an indication that the requested operation is a success when the expected data value matches the register data value; and

providing an indication that the requested operation is a failure when the expected data value does not match the register data value.

15. The method of claim 14 , further comprising randomizing the instruction sequence prior to issuance of the sequence to the corresponding instruction queue.

16. The method of claim 15 , wherein the randomization is based, at least in part on a constraint.

17. The method of claim 16 , wherein the constraint specifies an order of an order dependent instruction.