Track-and-hold circuit and A/D converter

1. A track-and-hold circuit comprising:

a first sampling circuit that samples an analog input signal;

a second sampling circuit that samples the analog input signal, the second sampling circuit and the first sampling circuit being connected in parallel;

a first differential amplifier that amplifies a signal output from the first sampling circuit; and

a second differential amplifier that amplifies a signal output from the second sampling circuit,

wherein each of said first and second differential amplifiers comprise first and second output nodes and a reset switch provided between the first and the second output nodes.

2. The track-and-hold circuit according to claim 1 , wherein each of the first and the second sampling circuits comprises:

a sampling switch that supplies the analog input signal; and

a sampling capacitor that samples and holds the analog input signal input through the sampling switch.

3. The track-and-hold circuit according to claim 2 , wherein the first and the second amplifiers are differential amplifiers that each comprises first and second input transistors, and the sampling capacitor is a gate capacitor of the first input transistor.

4. The track-and-hold circuit according to claim 3 , wherein a certain reference voltage is applied to a control electrode of the second input transistor.

5. The track-and-hold circuit according to claim 2 ,

wherein the sampling capacitor of the first sampling circuit forms a gate capacitor of the first differential amplifier, and

wherein the sampling capacitor of the second sampling circuit forms a gate capacitor of the second differential amplifier.

6. The track-and-hold circuit according to claim 1 ,

wherein each of the first and the second sampling circuits comprises a sampling switch that supplies the analog input signal, an ON/OFF of the sampling switching being synchronized with an ON/OFF of the reset switch.

7. The track-and-hold circuit according to claim 6 , wherein the sampling switch is ON while the reset switch is ON, and the sampling switch is OFF while the reset switch is OFF.

8. The track-and-hold circuit according to claim 1 , wherein an offset adjustment circuit is provided between the first and the second output nodes.

9. The track-and-hold circuit according to claim 8 , wherein the offset adjustment circuit is a current-cell type D/A converter.

10. The track-and-hold circuit according to claim 1 , wherein the track-and-hold circuit is operated when clock frequency is 2 GHz or more.

11. An A/D converter that comprises the track-and-hold circuit according to claim 1 .